公开(公告)号：US20180091815A1

公开(公告)日：2018-03-29

申请号：US15275373

申请日：2016-09-24

Applicant: Apple Inc.

Inventor： Abheek Banerjee ,  Syed Muhammad A. Rizvi ,  Yaxiong Zhou ,  Sorin C. Cismas

IPC: H04N19/13 ,  H04N19/70 ,  H04N19/21 ,  H04N19/436

CPC classification number: H04N19/13 ,  H04N19/21 ,  H04N19/42 ,  H04N19/436 ,  H04N19/44 ,  H04N19/70 ,  H04N19/91

Abstract: Systems and methods for improving decoding of encoded image data using parallel multi-bin decoding are provided. In one embodiment, multiple context bins per cycle are decoded for a set of syntax elements, by decoupling and/or retiming particular syntax parsing and/or arithmetic decoding tasks of the decoding process.

公开(公告)号：US11778211B2

公开(公告)日：2023-10-03

申请号：US17476704

申请日：2021-09-16

Applicant: Apple Inc.

Inventor： Yaxiong Zhou ,  Felix C. Fernandes ,  Jeffrey J. Irwin ,  Liviu R. Morogan ,  Sorin Constantin Cismas

IPC: H04N19/436 ,  H04N19/423

CPC classification number: H04N19/436 ,  H04N19/423

Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.

公开(公告)号：US20230081975A1

公开(公告)日：2023-03-16

申请号：US17476704

申请日：2021-09-16

Applicant: Apple Inc.

Inventor： Yaxiong Zhou ,  Felix C. Fernandes ,  Jeffrey J. Irwin ,  Liviu R. Morogan ,  Sorin Constantin Cismas

IPC: H04N19/436 ,  H04N19/423

Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.

公开(公告)号：US20220103844A1

公开(公告)日：2022-03-31

申请号：US17547001

申请日：2021-12-09

Applicant: Apple Inc.

Inventor： Athanasios Leontaris ,  Yaxiong Zhou ,  Francesco Iacopino

IPC: H04N19/40 ,  H04N19/184 ,  H04N19/146 ,  H04N19/91

Abstract: An electronic device includes a video encoding pipeline configured to encode source image data. The video encoding pipeline includes a first transcode engine and a second transcode engine. The electronic device also includes processing circuitry configured to determine a target throughput for a bin stream and determine whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines based on the target throughput. The processing circuitry is also configured to cause only the first transcode engine to encode the bin stream or both the first and second transcode engines to encode the bin stream based on determining whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines.

公开(公告)号：US10264264B2

公开(公告)日：2019-04-16

申请号：US15275373

申请日：2016-09-24

Applicant: Apple Inc.

Inventor： Abheek Banerjee ,  Syed Muhammad A. Rizvi ,  Yaxiong Zhou ,  Sorin C. Cismas

IPC: H04N19/44 ,  H04N19/42 ,  H04N19/13 ,  H04N19/21 ,  H04N19/436 ,  H04N19/70 ,  H04N19/91

Abstract: Systems and methods for improving decoding of encoded image data using parallel multi-bin decoding are provided. In one embodiment, multiple context bins per cycle are decoded for a set of syntax elements, by decoupling and/or retiming particular syntax parsing and/or arithmetic decoding tasks of the decoding process.

公开(公告)号：US11716480B2

公开(公告)日：2023-08-01

申请号：US17547001

申请日：2021-12-09

Applicant: Apple Inc.

Inventor： Athanasios Leontaris ,  Yaxiong Zhou ,  Francesco Iacopino

IPC: H04N19/40 ,  H04N19/184 ,  H04N19/146 ,  H04N19/91

CPC classification number: H04N19/40 ,  H04N19/146 ,  H04N19/184 ,  H04N19/91

Abstract: An electronic device includes a video encoding pipeline configured to encode source image data. The video encoding pipeline includes a first transcode engine and a second transcode engine. The electronic device also includes processing circuitry configured to determine a target throughput for a bin stream and determine whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines based on the target throughput. The processing circuitry is also configured to cause only the first transcode engine to encode the bin stream or both the first and second transcode engines to encode the bin stream based on determining whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines.

公开(公告)号：US11206415B1

公开(公告)日：2021-12-21

申请号：US17020708

申请日：2020-09-14

Applicant: Apple Inc.

Inventor： Athanasios Leontaris ,  Yaxiong Zhou ,  Francesco Iacopino

IPC: H04N19/40 ,  H04N19/184 ,  H04N19/146 ,  H04N19/91

Abstract: An electronic device includes a video encoding pipeline configured to encode source image data. The video encoding pipeline includes a first transcode engine and a second transcode engine. The electronic device also includes processing circuitry configured to determine a target throughput for a bin stream and determine whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines based on the target throughput. The processing circuitry is also configured to cause only the first transcode engine to encode the bin stream or both the first and second transcode engines to encode the bin stream based on determining whether to encode the bin stream using only the first transcode engine or both the first and second transcode engines.