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公开(公告)号：US20150310900A1
公开(公告)日：2015-10-29
申请号：US14262298
申请日：2014-04-25
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Jeffrey J. Irwin , Peter F. Holland
IPC: G11C7/10
CPC classification number: G09G5/363 , G09G2330/021 , G09G2360/128 , G09G2370/20
Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.
Abstract translation: 用于在显示管道中聚合具有机会主义的存储器请求的系统，装置和方法。 存储器请求被聚合在显示管道中的多个请求者的每个请求者。 当给定请求者的存储器请求数达到相应的阈值时，可以为给定的请求者发出存储器请求。 响应于确定给定请求者已经达到其阈值，其他请求者可以发出存储器请求，即使它们尚未聚合足够的存储器请求来达到其相应的阈值。
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公开(公告)号：US20230353339A1
公开(公告)日：2023-11-02
申请号：US18311129
申请日：2023-05-02
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
CPC classification number: H04L7/0016 , H04L7/0008 , G06F1/12
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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公开(公告)号：US09412147B2
公开(公告)日：2016-08-09
申请号：US14493755
申请日：2014-09-23
Applicant: Apple Inc.
Inventor： Peter F. Holland , Hari Ganesh R. Thirunageswaram , Jeffrey J. Irwin
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28 , G09G5/363 , G09G5/395 , G09G2320/0276 , G09G2340/0407 , G09G2340/10 , G09G2352/00 , G09G2360/121
Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.
Abstract translation: 用于处理图形数据的装置可以包括多个处理流水线，每个流水线被配置为接收和处理像素数据。 功能单元可以组合每个处理流水线的输出。 包括在给定处理流水线中的缓冲器可以被配置为响应于确定给定处理流水线不活动而存储来自功能单元的数据。 然后，缓冲器可以将存储的数据发送到存储器。
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公开(公告)号：US20160086298A1
公开(公告)日：2016-03-24
申请号：US14493755
申请日：2014-09-23
Applicant: Apple Inc.
Inventor： Peter F. Holland , Hari Ganesh R. Thirunageswaram , Jeffrey J. Irwin
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28 , G09G5/363 , G09G5/395 , G09G2320/0276 , G09G2340/0407 , G09G2340/10 , G09G2352/00 , G09G2360/121
Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.
Abstract translation: 用于处理图形数据的装置可以包括多个处理流水线，每个流水线被配置为接收和处理像素数据。 功能单元可以组合每个处理流水线的输出。 包括在给定处理流水线中的缓冲器可以被配置为响应于确定给定处理流水线不活动而存储来自功能单元的数据。 然后，缓冲器可以将存储的数据发送到存储器。
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公开(公告)号：US12028437B2
公开(公告)日：2024-07-02
申请号：US18311129
申请日：2023-05-02
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
CPC classification number: H04L7/0016 , G06F1/12 , H04L7/0008
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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Patent Agency Ranking
公开(公告)号：US20220085969A1
公开(公告)日：2022-03-17
申请号：US17472242
申请日：2021-09-10
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
IPC: H04L7/00
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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公开(公告)号：US11778211B2
公开(公告)日：2023-10-03
申请号：US17476704
申请日：2021-09-16
Applicant: Apple Inc.
Inventor： Yaxiong Zhou , Felix C. Fernandes , Jeffrey J. Irwin , Liviu R. Morogan , Sorin Constantin Cismas
IPC: H04N19/436 , H04N19/423
CPC classification number: H04N19/436 , H04N19/423
Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.
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公开(公告)号：US20230081975A1
公开(公告)日：2023-03-16
申请号：US17476704
申请日：2021-09-16
Applicant: Apple Inc.
Inventor： Yaxiong Zhou , Felix C. Fernandes , Jeffrey J. Irwin , Liviu R. Morogan , Sorin Constantin Cismas
IPC: H04N19/436 , H04N19/423
Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.
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公开(公告)号：US10546558B2
公开(公告)日：2020-01-28
申请号：US14262298
申请日：2014-04-25
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Jeffrey J. Irwin , Peter F. Holland
IPC: G09G5/36
Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.
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公开(公告)号：US20240372692A1
公开(公告)日：2024-11-07
申请号：US18676210
申请日：2024-05-28
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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