Floating-Point Multiply-Add with Down-Conversion

    公开(公告)号:US20170293470A1

    公开(公告)日:2017-10-12

    申请号:US15092401

    申请日:2016-04-06

    Applicant: Apple Inc.

    CPC classification number: G06F7/483 G06F7/5443

    Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.

    Elevator scenario detection and operation for wireless devices

    公开(公告)号:US11166215B2

    公开(公告)日:2021-11-02

    申请号:US16882085

    申请日:2020-05-22

    Applicant: Apple Inc.

    Abstract: This disclosure relates to techniques for a wireless device to detect and operate in an elevator or elevator-like conditions. The wireless device may establish a cellular link with a cellular base station. One or more conditions associated with being in an elevator may be detected. The wireless device may determine to operate in an elevator mode based at least in part on detecting the one or more conditions associated with being in an elevator. The wireless device may operate in the elevator mode. One or more conditions associated with exiting an elevator may be detected. The wireless device may determine to operate in a normal mode based at least in part on detecting the one or more conditions associated with exiting an elevator. The wireless device may operate in the normal mode.

    Multi-path fused multiply-add with power control

    公开(公告)号:US10481869B1

    公开(公告)日:2019-11-19

    申请号:US15809648

    申请日:2017-11-10

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to circuitry configured to perform floating-point operations such as fused multiply-addition (FMA) with multiple paths and power control. In some embodiments, an FMA unit includes a near path and multiple far paths and is configured to select a path based on a determined exponent difference. In some embodiments, the FMA unit is configured to operate portions of non-selected paths in a low power state.

    Elevator Scenario Detection and Operation for Wireless Devices

    公开(公告)号:US20200383024A1

    公开(公告)日:2020-12-03

    申请号:US16882085

    申请日:2020-05-22

    Applicant: Apple Inc.

    Abstract: This disclosure relates to techniques for a wireless device to detect and operate in an elevator or elevator-like conditions. The wireless device may establish a cellular link with a cellular base station. One or more conditions associated with being in an elevator may be detected. The wireless device may determine to operate in an elevator mode based at least in part on detecting the one or more conditions associated with being in an elevator. The wireless device may operate in the elevator mode. One or more conditions associated with exiting an elevator may be detected. The wireless device may determine to operate in a normal mode based at least in part on detecting the one or more conditions associated with exiting an elevator. The wireless device may operate in the normal mode.

    Floating-point multiply-add with down-conversion

    公开(公告)号:US10282169B2

    公开(公告)日:2019-05-07

    申请号:US15092401

    申请日:2016-04-06

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.

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