公开(公告)号：US11476081B2

公开(公告)日：2022-10-18

申请号：US16917304

申请日：2020-06-30

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Vadim Vereschagin ,  Assaf Shamir ,  Elad Sommer ,  Sharon Duvdevani-Bar ,  Meng Li Cecilia Lim

IPC: H01L27/11519 ,  H01L27/11551 ,  H01L27/11524 ,  H01L21/66 ,  H01J37/22 ,  H01J37/28

Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

公开(公告)号：US11651509B2

公开(公告)日：2023-05-16

申请号：US17281948

申请日：2019-10-31

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Roi Meir ,  Sahar Levin ,  Ishai Schwarzband ,  Grigory Klebanov ,  Shimon Levi ,  Efrat Noifeld ,  Hiroshi Miroku ,  Taku Yoshizawa ,  Kasturi Saha ,  Sharon Duvdevani-Bar ,  Vadim Vereschagin

IPC: G06T7/00 ,  G06T7/13 ,  G06T7/194 ,  G06T7/60 ,  G06V10/44 ,  G06V20/69 ,  G01N23/225

CPC classification number: G06T7/0004 ,  G01N23/225 ,  G06T7/13 ,  G06T7/194 ,  G06T7/60 ,  G06V10/44 ,  G06V20/695 ,  G01N2223/401 ,  G06T2207/10061 ,  G06T2207/30148

Abstract: A method for process control of a semiconductor structure fabricated by a series of fabrication steps, the method comprising obtaining an image of the semiconductor structure indicative of at least two individual fabrication steps; wherein the image is generated by scanning the semiconductor structure with a charged particle beam and collecting signals emanating from the semiconductor structure; and processing, by a hardware processor, the image to determining a parameter of the semiconductor structure, wherein processing includes measuring step/s from among the fabrication steps as an individual feature.

公开(公告)号：US20210066026A1

公开(公告)日：2021-03-04

申请号：US16917304

申请日：2020-06-30

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Vadim Vereschagin ,  Assaf Shamir ,  Elad Sommer ,  Sharon Duvdevani-Bar ,  Meng Li Cecilia Lim

IPC: H01J37/22 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01J37/28

Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

公开(公告)号：US11443420B2

公开(公告)日：2022-09-13

申请号：US17135939

申请日：2020-12-28

Applicant: Applied Materials Israel Ltd.

Inventor： Roman Kris ,  Grigory Klebanov ,  Einat Frishman ,  Tal Orenstein ,  Meir Vengrover ,  Noa Marom ,  Ilan Ben-Harush ,  Rafael Bistritzer ,  Sharon Duvdevani-Bar

IPC: G06T7/00 ,  G03F7/20 ,  G01N21/95

Abstract: There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.

公开(公告)号：US11056404B1

公开(公告)日：2021-07-06

申请号：US16719856

申请日：2019-12-18

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Grigory Klebanov ,  Dhananjay Singh Rathore ,  Einat Frishman ,  Sharon Duvdevani-Bar ,  Assaf Shamir ,  Elad Sommer ,  Jannelle Anna Geva ,  Daniel Alan Rogers ,  Ido Friedler ,  Avi Aviad Ben Simhon

IPC: G06T7/00 ,  H01L21/66

Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.

公开(公告)号：US20210193536A1

公开(公告)日：2021-06-24

申请号：US16719856

申请日：2019-12-18

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Grigory Klebanov ,  Dhananjay Singh Rathore ,  Einat Frishman ,  Sharon Duvdevani-Bar ,  Assaf Shamir ,  Elad Sommer ,  Jannelle Anna Geva ,  Daniel Alan Rogers ,  Ido Friedler ,  Avi Aviad Ben Simhon

IPC: H01L21/66 ,  G06T7/00

Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.