公开(公告)号：US20210066026A1

公开(公告)日：2021-03-04

申请号：US16917304

申请日：2020-06-30

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Vadim Vereschagin ,  Assaf Shamir ,  Elad Sommer ,  Sharon Duvdevani-Bar ,  Meng Li Cecilia Lim

IPC: H01J37/22 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01J37/28

Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

公开(公告)号：US11476081B2

公开(公告)日：2022-10-18

申请号：US16917304

申请日：2020-06-30

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Vadim Vereschagin ,  Assaf Shamir ,  Elad Sommer ,  Sharon Duvdevani-Bar ,  Meng Li Cecilia Lim

IPC: H01L27/11519 ,  H01L27/11551 ,  H01L27/11524 ,  H01L21/66 ,  H01J37/22 ,  H01J37/28

Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

公开(公告)号：US11686571B2

公开(公告)日：2023-06-27

申请号：US17465753

申请日：2021-09-02

Applicant: Applied Materials Israel Ltd.

Inventor： Roman Kris ,  Ilan Ben-Harush ,  Rafael Bistritzer ,  Vadim Vereschagin ,  Elad Sommer ,  Grigory Klebanov ,  Arundeepth Thamarassery ,  Jannelle Anna Geva ,  Gal Daniel Gutterman ,  Einat Frishman ,  Sahar Levin

IPC: G01B11/24 ,  G01B9/02 ,  G06T7/00

CPC classification number: G01B9/02043 ,  G01B9/02084 ,  G01B11/24 ,  G06T7/001 ,  G06T2207/30148

Abstract: There is provided a system and method of a method of detecting a local shape deviation of a structural element in a semiconductor specimen, comprising: obtaining an image comprising an image representation of the structural element; extracting, from the image, an actual contour of the image representation; estimating a reference contour of the image representation indicative of a standard shape of the structural element, wherein the reference contour is estimated based on a Fourier descriptor representative of the reference contour, the Fourier descriptor being estimated using an optimization method based on a loss function specifically selected to be insensitive to local shape deviation of the actual contour; and performing one or more measurements representative of one or more differences between the actual contour and the reference contour, the measurements indicative of whether a local shape deviation is present in the structural element.

公开(公告)号：US11056404B1

公开(公告)日：2021-07-06

申请号：US16719856

申请日：2019-12-18

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Grigory Klebanov ,  Dhananjay Singh Rathore ,  Einat Frishman ,  Sharon Duvdevani-Bar ,  Assaf Shamir ,  Elad Sommer ,  Jannelle Anna Geva ,  Daniel Alan Rogers ,  Ido Friedler ,  Avi Aviad Ben Simhon

IPC: G06T7/00 ,  H01L21/66

Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.

公开(公告)号：US20210193536A1

公开(公告)日：2021-06-24

申请号：US16719856

申请日：2019-12-18

Applicant: APPLIED MATERIALS ISRAEL LTD.

Inventor： Roman Kris ,  Grigory Klebanov ,  Dhananjay Singh Rathore ,  Einat Frishman ,  Sharon Duvdevani-Bar ,  Assaf Shamir ,  Elad Sommer ,  Jannelle Anna Geva ,  Daniel Alan Rogers ,  Ido Friedler ,  Avi Aviad Ben Simhon

IPC: H01L21/66 ,  G06T7/00

Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.