公开(公告)号：US20240078323A1

公开(公告)日：2024-03-07

申请号：US18446528

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Alexander Klimov ,  Andreas Lars Sandberg ,  Roberto Avanzi

IPC: G06F21/60 ,  G06F21/74

CPC classification number: G06F21/602 ,  G06F21/74

Abstract: An apparatus comprises counter tree circuitry configured to store, in a first node of a counter tree, a representation of a parent counter value and in a second node of the counter tree, wherein the second node is a child node of the first node, an encrypted representation of two or more counter values. The encryption operation for forming the encrypted representation of the two or more counter values takes as an input the parent counter value. The apparatus also comprises integrity checking circuitry to check the integrity of an item of data retrieved from memory based on a comparison between a stored authentication code and a generated authentication code generated based on the item of data and a decrypted counter value determined from an encrypted representation of a counter value retrieved from the second node, decrypted using a parent counter value retrieved from the first node.

公开(公告)号：US11720683B2

公开(公告)日：2023-08-08

申请号：US17192278

申请日：2021-03-04

Applicant: Arm Limited

Inventor： Rainer Herberholz ,  Alexander Klimov ,  Peter Andrew Rees Williams

IPC: G06F21/57 ,  G06F8/65 ,  H04L9/32

CPC classification number: G06F21/575 ,  G06F8/65 ,  G06F21/572 ,  H04L9/3236 ,  G06F2221/033

Abstract: Embodiments of the present disclosure advantageously provide a secure boot integrity verification system that is protected against future quantum attacks without relying on correctly functioning hardware security modules (HSMs) for the expected lifetime of the computer system or embedded device.

公开(公告)号：US11681621B2

公开(公告)日：2023-06-20

申请号：US17471406

申请日：2021-09-10

Applicant: Arm Limited

Inventor： Alexander Klimov

IPC: G06F12/0811 ,  G06F12/0877 ,  G06F12/0817

CPC classification number: G06F12/0811 ,  G06F12/082 ,  G06F12/0877

Abstract: Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.

公开(公告)号：US20240080193A1

公开(公告)日：2024-03-07

申请号：US18446530

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Roberto Avanzi ,  Alexander Klimov

IPC: H04L9/32

CPC classification number: H04L9/32

Abstract: An apparatus comprises counter integrity tree circuitry to maintain a counter integrity tree having a plurality of nodes. The counter integrity tree circuitry is configured to store, in a first node of the counter integrity tree, an encrypted representation of two or more non-repeating counters and in a second, parent, node, an indication of a function value equal to a non-repeating function of the two or more non-repeating counters of the first node. The apparatus comprises integrity checking circuitry configured to check the integrity of the first node using the function value retrieved from the second node.

公开(公告)号：US11681617B2

公开(公告)日：2023-06-20

申请号：US17199864

申请日：2021-03-12

Applicant: Arm Limited

Inventor： Alexander Klimov

IPC: G06F12/0802 ,  G06F21/60 ,  G06F21/62 ,  G06F21/64

CPC classification number: G06F12/0802 ,  G06F21/602 ,  G06F21/62 ,  G06F21/64 ,  G06F2212/60

Abstract: A data processing apparatus includes a requester, a completer and a cache. Data is transferred between the requester and the cache and between the cache and the completer. The cache implements a cache eviction policy. The completer determines an eviction cost associated with evicting the data from the cache and notifies the cache of the eviction cost. The cache eviction policy implemented by the cache is based, at least in part, on the cost of evicting the data from the cache. The eviction cost may be determined, for example, based on properties or usage of a memory system of the completer.

公开(公告)号：US20230079210A1

公开(公告)日：2023-03-16

申请号：US17471406

申请日：2021-09-10

Applicant: Arm Limited

Inventor： Alexander Klimov

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/0877

Abstract: Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.

公开(公告)号：US20220292015A1

公开(公告)日：2022-09-15

申请号：US17199864

申请日：2021-03-12

Applicant: Arm Limited

Inventor： Alexander Klimov

IPC: G06F12/0802 ,  G06F21/60 ,  G06F21/64 ,  G06F21/62

Abstract: A data processing apparatus includes a requester, a completer and a cache. Data is transferred between the requester and the cache and between the cache and the completer. The cache implements a cache eviction policy. The completer determines an eviction cost associated with evicting the data from the cache and notifies the cache of the eviction cost. The cache eviction policy implemented by the cache is based, at least in part, on the cost of evicting the data from the cache. The eviction cost may be determined, for example, based on properties or usage of a memory system of the completer.

公开(公告)号：US20220284104A1

公开(公告)日：2022-09-08

申请号：US17192278

申请日：2021-03-04

Applicant: Arm Limited

Inventor： Rainer Herberholz ,  Alexander Klimov ,  Peter Andrew Rees Williams

IPC: G06F21/57 ,  H04L9/32 ,  G06F8/65

Abstract: Embodiments of the present disclosure advantageously provide a secure boot integrity verification system that is protected against future quantum attacks without relying on correctly functioning hardware security modules (HSMs) for the expected lifetime of the computer system or embedded device.