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公开(公告)号：US20240078323A1
公开(公告)日：2024-03-07
申请号：US18446528
申请日：2023-08-09
Applicant: Arm Limited
Inventor： Alexander Klimov , Andreas Lars Sandberg , Roberto Avanzi
CPC classification number: G06F21/602 , G06F21/74
Abstract: An apparatus comprises counter tree circuitry configured to store, in a first node of a counter tree, a representation of a parent counter value and in a second node of the counter tree, wherein the second node is a child node of the first node, an encrypted representation of two or more counter values. The encryption operation for forming the encrypted representation of the two or more counter values takes as an input the parent counter value. The apparatus also comprises integrity checking circuitry to check the integrity of an item of data retrieved from memory based on a comparison between a stored authentication code and a generated authentication code generated based on the item of data and a decrypted counter value determined from an encrypted representation of a counter value retrieved from the second node, decrypted using a parent counter value retrieved from the first node.
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公开(公告)号：US12010242B2
公开(公告)日：2024-06-11
申请号：US16925723
申请日：2020-07-10
Applicant: Arm Limited
Inventor： Roberto Avanzi , Andreas Lars Sandberg , Michael Andrew Campbell , Matthias Lothar Boettcher , Prakash S. Ramrakhyani
CPC classification number: H04L9/3242 , G06F21/57 , G06F21/64 , H04W12/06 , G06F12/0875 , G06F12/1408 , G06F21/79
Abstract: To protect the integrity of data stored in a protected area of memory, data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs. The integrity of the first data block is contingent on the verification authentication code matching the retrieved authentication code.
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公开(公告)号：US11775177B2
公开(公告)日：2023-10-03
申请号：US17269919
申请日：2019-10-17
Applicant: Arm Limited
Inventor： Yuval Elad , Roberto Avanzi , Jason Parker
IPC: G06F3/06 , G06F16/901 , G06F12/1009
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F12/1009 , G06F16/9027
Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.
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Patent Agency Ranking
公开(公告)号：US10733313B2
公开(公告)日：2020-08-04
申请号：US15892770
申请日：2018-02-09
Applicant: Arm Limited
Inventor： Prakash S. Ramrakhyani , Roberto Avanzi , Wendy Arnott Elsasser
Abstract: A counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree.
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公开(公告)号：US20190251275A1
公开(公告)日：2019-08-15
申请号：US15892770
申请日：2018-02-09
Applicant: Arm Limited
Inventor： Prakash S. Ramrakhyani , Roberto Avanzi , Wendy Arnott Elsasser
Abstract: A counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree.
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公开(公告)号：US12124711B2
公开(公告)日：2024-10-22
申请号：US17944553
申请日：2022-09-14
Applicant: Arm Limited
Inventor： Roberto Avanzi
IPC: G06F3/06
CPC classification number: G06F3/0623 , G06F3/0659 , G06F3/0673
Abstract: Apparatus, methods, and software for protecting a plurality of memory locations are disclosed. Logical addresses are translated into physical addresses in dependence on one of a first translation function and a second translation function. A transitional logical address and an associated transitional value are locally held in circuitry which applies the translation functions. A remapping of first to second translation function usage is performed by determining a new transitional physical address by applying the second translation function to the transitional logical address; determining a new transitional logical address by applying an inverse of the first translation function to the new transitional physical address; retrieving a new transitional value using the new transitional physical address; storing the old transitional value to the memory location indicated by the new transitional physical address; and locally storing the new transitional value. This remapping can be interleaved with normal memory accesses.
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公开(公告)号：US12073104B1
公开(公告)日：2024-08-27
申请号：US18299763
申请日：2023-04-13
Applicant: Arm Limited
Inventor： Roberto Avanzi , Andreas Lars Sandberg , David Helmut Schall
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0623 , G06F3/0673
Abstract: There is provided a memory protection unit configured to maintain region metadata associated with storage regions of off-chip storage and protection metadata associated with each of the storage regions. The protection metadata is stored in the off-chip storage, and the region metadata encodes whether each of the storage regions belongs to a set of protected storage regions or to a set of unprotected storage regions and encodes information indicating corresponding protection metadata associated with each storage region. The memory protection unit is configured to update the region metadata in response to a region update request identifying a given storage region for which the region metadata is to be modified and to dynamically adjust an amount of memory required to store protection metadata associated with the set of protected storage regions in response to the update to the region metadata.
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公开(公告)号：US20240080193A1
公开(公告)日：2024-03-07
申请号：US18446530
申请日：2023-08-09
Applicant: Arm Limited
Inventor： Andreas Lars Sandberg , Roberto Avanzi , Alexander Klimov
IPC: H04L9/32
CPC classification number: H04L9/32
Abstract: An apparatus comprises counter integrity tree circuitry to maintain a counter integrity tree having a plurality of nodes. The counter integrity tree circuitry is configured to store, in a first node of the counter integrity tree, an encrypted representation of two or more non-repeating counters and in a second, parent, node, an indication of a function value equal to a non-repeating function of the two or more non-repeating counters of the first node. The apparatus comprises integrity checking circuitry configured to check the integrity of the first node using the function value retrieved from the second node.
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