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公开(公告)号：US20200371749A1
公开(公告)日：2020-11-26
申请号：US16417866
申请日：2019-05-21
Applicant: Arm Limited
Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.
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公开(公告)号：US20190196832A1
公开(公告)日：2019-06-27
申请号：US15855139
申请日：2017-12-27
Applicant: Arm Limited
Inventor： Vladimir VASEKIN , Chiloda Ashan Senarath PATHIRANE , Jungsoo KIM , Alexei FEDOROV
CPC classification number: G06F9/30196 , G06F9/3802 , G06F9/3867
Abstract: A data processing system 2 includes an instruction pipeline 14 containing instruction queue circuitry 28, fusion circuitry 30 and decoder circuitry 32. The fusion circuitry 30 serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry 32 which decodes X program instructions in parallel using parallel decoders 40, 42, 44.
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3.发明申请公开(公告)号：US20200019402A1
公开(公告)日：2020-01-16
申请号：US16030963
申请日：2018-07-10
Applicant: Arm Limited
Inventor： Karel Hubertus Gerardus WALTERS , Chiloda Ashan Senarath PATHIRANE , Michael Alexander KENNEDY
IPC: G06F9/30
Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.
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公开(公告)号：US20170199738A1
公开(公告)日：2017-07-13
申请号：US14989841
申请日：2016-01-07
Applicant: ARM LIMITED
Inventor： Vladimir VASEKIN , Antony John PENTON , Chiloda Ashan Senarath PATHIRANE , Andrew James Antony LEES
IPC: G06F9/30
CPC classification number: G06F9/3836 , G06F9/384 , G06F9/3851
Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.
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Patent Agency Ranking
5.发明申请公开(公告)号：US20170139716A1
公开(公告)日：2017-05-18
申请号：US14944803
申请日：2015-11-18
Applicant: ARM Limited
IPC: G06F9/38
CPC classification number: G06F9/3851
Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.
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公开(公告)号：US20170132010A1
公开(公告)日：2017-05-11
申请号：US14938285
申请日：2015-11-11
Applicant: ARM LIMITED
IPC: G06F9/38
CPC classification number: G06F9/3855 , G06F9/384
Abstract: An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.
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公开(公告)号：US20210096863A1
公开(公告)日：2021-04-01
申请号：US16583729
申请日：2019-09-26
Applicant: Arm Limited
Inventor： Chiloda Ashan Senarath PATHIRANE
Abstract: Aspects of the present disclosure relate to an apparatus comprising register circuitry implementing a plurality of registers and processing circuitry to perform data processing operations on data stored in said registers. The apparatus comprises store buffer circuitry to, responsive to a store instruction in respect of given data, temporarily store said given data prior to providing said given data to a memory. Responsive to receiving at the processing circuitry a request to perform a state-saving-triggering operation, the register circuitry is configured to capture in shadow registers of said register circuitry a state of a subset of registers of the plurality of registers, provide the captured state from the shadow registers to the memory.
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公开(公告)号：US20200004547A1
公开(公告)日：2020-01-02
申请号：US16021178
申请日：2018-06-28
Applicant: Arm Limited
Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry. The request issued from the processing unit includes a signature value indicative of the predicted result value, and the result producing structure references the signature value in order to detect whether a mispredict condition exists indicating that the predicted result value differs from the result value. The apparatus further provides a mispredict signal transmission path via which the result producing structure, when the mispredict condition is detected, can assert a mispredict signal for receipt by the processing unit prior to the result value being available to the processing unit. Such an approach can reduce the misprediction penalty associated with using a mispredicted result value.
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9.发明申请公开(公告)号：US20180267805A1
公开(公告)日：2018-09-20
申请号：US15987113
申请日：2018-05-23
Applicant: ARM Limited
IPC: G06F9/38
CPC classification number: G06F9/3851
Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.
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