公开(公告)号：US20190196832A1

公开(公告)日：2019-06-27

申请号：US15855139

申请日：2017-12-27

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  Chiloda Ashan Senarath PATHIRANE ,  Jungsoo KIM ,  Alexei FEDOROV

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30196 ,  G06F9/3802 ,  G06F9/3867

Abstract: A data processing system 2 includes an instruction pipeline 14 containing instruction queue circuitry 28, fusion circuitry 30 and decoder circuitry 32. The fusion circuitry 30 serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry 32 which decodes X program instructions in parallel using parallel decoders 40, 42, 44.

公开(公告)号：US20240020237A1

公开(公告)日：2024-01-18

申请号：US17864625

申请日：2022-07-14

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Jungsoo KIM ,  James David DUNDAS ,  . ABHISHEK RAJA

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: There is provided a data processing apparatus in which receive circuitry receives a result signal from a lower level cache and a higher level cache in respect of a first instruction block. The lower level cache and the higher level cache are arranged hierarchically and transmit circuitry transmits, to the higher level cache, a query for the result signal. In response to the result signal originating from the higher level cache containing requested data, the transmit circuitry transmits a further query to the higher level cache for a subsequent instruction block at an earlier time than the further query is transmitted to the higher level cache when the result signal containing the requested data originates from the lower level cache.

公开(公告)号：US20230297384A1

公开(公告)日：2023-09-21

申请号：US17699326

申请日：2022-03-21

Applicant: Arm Limited

Inventor： Nicholas Andrew PLANTE ,  Joseph Michael PUSDESRIS ,  Jungsoo KIM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30181 ,  G06F9/30079 ,  G06F9/30029

Abstract: A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result.