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公开(公告)号：US20210271512A1
公开(公告)日：2021-09-02
申请号：US17056896
申请日：2019-05-01
Applicant: Arm Limited
Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.
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公开(公告)号：US20200371749A1
公开(公告)日：2020-11-26
申请号：US16417866
申请日：2019-05-21
Applicant: Arm Limited
Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.
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公开(公告)号：US20140108691A1
公开(公告)日：2014-04-17
申请号：US13653472
申请日：2012-10-17
Applicant: ARM LIMITED
Inventor： Michael Alexander KENNEDY , Anthony JEBSON
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/5027
Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.
Abstract translation: 数据处理装置具有多个处理器和多个中断接口，每个中断接口用于处理来自相应处理器的中断请求。 中断分配器控制中断请求到中断接口的路由。 共享中断请求可由多个处理器使用。 响应于共享中断请求，目标中断接口向中断分配器发出中断所有权请求，如果它估计相应的处理器可用于维护共享中断请求，则不会将共享中断请求传递给相应的处理器。 当从中断分配器接收到所有权确认，指示处理器被选择用于维护共享中断请求时，共享中断请求被传递给相应的处理器。
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4.发明申请公开(公告)号：US20200019402A1
公开(公告)日：2020-01-16
申请号：US16030963
申请日：2018-07-10
Applicant: Arm Limited
Inventor： Karel Hubertus Gerardus WALTERS , Chiloda Ashan Senarath PATHIRANE , Michael Alexander KENNEDY
IPC: G06F9/30
Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.
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Patent Agency Ranking
公开(公告)号：US20180307489A1
公开(公告)日：2018-10-25
申请号：US15859931
申请日：2018-01-02
Applicant: Arm Limited
Inventor： Michael Alexander KENNEDY , Neil BURGESS
IPC: G06F9/30
CPC classification number: G06F9/30196 , G06F7/5443 , G06F9/3001 , G06F9/30032 , G06F9/30036
Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E
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公开(公告)号：US20140351472A1
公开(公告)日：2014-11-27
申请号：US13900777
申请日：2013-05-23
Applicant: ARM LIMITED
Inventor： Anthony JEBSON , Richard Roy GRISENTHWAITE , Michael Alexander KENNEDY , Ian Michael CAULFIELD
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/4818
Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.
Abstract translation: 数据处理装置包括多个系统寄存器和一组用于控制进入中断的处理的中断处理寄存器。 所述设备还包括被配置为执行所述多个执行级别的软件的处理电路，以及被配置为将所述输入中断路由到中断处理软件的中断控制器电路，所述中断处理软件被配置为在所述多个执行级中的一个执行级别运行，并且将访问控制电路 配置为根据所述多个执行级别中的一个来动态地控制对至少一些所述中断处理寄存器的访问，所述多个执行级别中的所述进入中断被路由到。 配置为在特定执行级别运行的中断处理软件无法访问中断处理寄存器，用于处理被配置为以更特权的执行级运行的中断处理软件的不同输入中断。
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公开(公告)号：US20240004611A1
公开(公告)日：2024-01-04
申请号：US17855856
申请日：2022-07-01
Applicant: Arm Limited
Inventor： Michael Alexander KENNEDY , Marco MONTAGNA , Karel Hubertus Gerardus WALTERS , Ian Michael CAULFIELD
IPC: G06F7/483
CPC classification number: G06F7/483
Abstract: Processing circuitry performs a processing operation to generate a two's complement result value representing a positive or negative number in two's complement representation. Normalization-and-rounding circuitry converts the two's complement result value to a normalized-and-rounded floating-point result value represented using sign-magnitude representation. The normalization-and-rounding circuitry comprises incrementing circuitry to perform an increment addition (e.g. a rounding increment or a conversion increment) to generate a fraction of the normalized-and-rounded floating-point result value. For an operation where the increment addition is required to be performed, tininess detection circuitry detects the after-rounding tininess status based on a still-to-be-incremented version of the normalized-and-rounded floating-point result value prior to the increment addition by the increment circuitry.
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公开(公告)号：US20200057609A1
公开(公告)日：2020-02-20
申请号：US16105066
申请日：2018-08-20
Applicant: Arm Limited
Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P≥3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.
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公开(公告)号：US20170192915A1
公开(公告)日：2017-07-06
申请号：US15464892
申请日：2017-03-21
Applicant: ARM Limited
Inventor： Michael Alexander KENNEDY , Anthony JEBSON
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/5027
Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.
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