公开(公告)号：US12175251B2

公开(公告)日：2024-12-24

申请号：US18107139

申请日：2023-02-08

Applicant: Arm Limited

Inventor： Glen Andrew Harris ,  Alexander Cole Shulyak ,  . Abhishek Raja ,  Bipin Prasad Heremagalur Ramaprasad ,  William Elton Burky ,  Li Ma ,  Michael David Achenbach ,  Nicholas Andrew Plante ,  Yasuo Ishii

IPC: G06F9/38

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

公开(公告)号：US11989583B2

公开(公告)日：2024-05-21

申请号：US17218425

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Chris Abernathy ,  Eric Charles Quinnell ,  Abhishek Raja ,  Michael David Achenbach

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/48 ,  G06F9/4843 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5038

Abstract: Circuitry comprises two or more clusters of execution units, each cluster comprising one or more execution units to execute processing instructions; and scheduler circuitry to maintain one or more queues of processing instructions, the scheduler circuitry comprising picker circuitry to select a queued processing instruction for issue to an execution unit of one of the clusters of execution units for execution; in which: the scheduler circuitry is configured to maintain dependency data associated with each queued processing instruction, the dependency data for a queued processing instruction indicating any source operands which are required to be available for use in execution of that queued processing instruction and to inhibit issue of that queued processing instruction until all of the required source operands for that queued processing instruction are available and is configured to be responsive to an indication to the scheduler circuitry of the availability of the given operand as a source operand for use in execution of queued processing instructions; and the scheduler circuitry is responsive to an indication of availability of one or more last awaited source operands for a given queued processing instruction, to inhibit issue by the scheduler circuitry of the given queued processing instruction to an execution unit in a cluster of execution units other than a cluster of execution units containing an execution unit which generated at least one of those last awaited source operands.

公开(公告)号：US11762664B2

公开(公告)日：2023-09-19

申请号：US17569157

申请日：2022-01-05

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Michael David Achenbach ,  David Gum Lim ,  Abhishek Raja

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3016 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3838

Abstract: There is provided a data processing apparatus comprising decode circuitry responsive to receipt of a block of instructions to generate control signals indicative of each of the block of instructions, and to analyse the block of instructions to detect a potential hazard instruction. The data processing apparatus is provided with decode circuitry to encode information indicative of a clean restart point into the control signals associated with the potential hazard instruction. The data processing apparatus is provided with data processing circuity to perform out-of-order execution of at least some of the block of instructions, and control circuitry responsive to a determination, at execution of the potential hazard instruction, that data values used as operands for the potential hazard instruction have been modified by out-of-order execution of a subsequent instruction, to restart execution from the clean restart point and to flush held data values from the data processing circuitry.

公开(公告)号：US11327791B2

公开(公告)日：2022-05-10

申请号：US16546752

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Michael David Achenbach ,  Robert Greg McDonald ,  Nicholas Andrew Pfister ,  Kelvin Domnic Goveas ,  Michael Filippo ,  . Abhishek Raja ,  Zachary Allen Kingsbury

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/52 ,  G06F9/50 ,  G06F9/30

Abstract: An apparatus provides an issue queue having a first section and a second section. Each entry in each section stores operation information identifying an operation to be performed. Allocation circuitry allocates each item of received operation information to an entry in the first section or the second section. Selection circuitry selects from the issue queue, during a given selection iteration, an operation from amongst the operations whose required source operands are available. Availability update circuitry updates source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. A deferral mechanism inhibits from selection, during a next selection iteration, any operation associated with an entry in the second section whose source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration.