公开(公告)号：US11693666B2

公开(公告)日：2023-07-04

申请号：US17505854

申请日：2021-10-20

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Nicholas Andrew Plante ,  Yasuo Ishii ,  Chris Abernathy

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC classification number: G06F9/3861 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/3455 ,  G06F9/3844 ,  G06F9/3848 ,  G06F9/3859

Abstract: A predicated-loop-terminating branch instruction controls, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a predicated loop body or process a following instruction. If at least one unnecessary iteration of the predicated loop body is processed following a mispredicted-non-termination branch misprediction when the loop termination condition is mispredicted as unsatisfied for a given iteration when it should have been satisfied, processing of the at least one unnecessary iteration of the predicated loop body is predicated to suppress an effect of the at least one unnecessary iteration. When the mispredicted-non-termination branch misprediction is detected for the given iteration of the predicated-loop-terminating branch instruction, in response to determining that a flush suppressing condition is satisfied, flushing of the at least one unnecessary iteration of the predicated loop body is suppressed as a response to the mispredicted-non-termination branch misprediction.

公开(公告)号：US12026515B2

公开(公告)日：2024-07-02

申请号：US17959556

申请日：2022-10-04

Applicant: Arm Limited

Inventor： William Elton Burky ,  Nicholas Andrew Plante ,  Alexander Cole Shulyak ,  Joshua David Knebel ,  Yasuo Ishii

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/3856

Abstract: A data processing apparatus includes detection circuitry that detects a parent instruction and a child instruction from a stream of instructions. The parent instruction references a destination register that is referenced as a source register by the child instruction. Adjustment circuitry then adjusts the child instruction to produce an adjusted child instruction whose behaviour is logically equivalent to a behaviour of executing the parent instruction followed by the child instruction.

公开(公告)号：US12204785B2

公开(公告)日：2025-01-21

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Steven Daniel Maclean ,  Nicholas Andrew Plante ,  Muhammad Umar Farooq ,  Michael Brian Schinzler ,  Nicholas Todd Humphries ,  Glen Andrew Harris

IPC: G06F3/06

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US12175251B2

公开(公告)日：2024-12-24

申请号：US18107139

申请日：2023-02-08

Applicant: Arm Limited

Inventor： Glen Andrew Harris ,  Alexander Cole Shulyak ,  . Abhishek Raja ,  Bipin Prasad Heremagalur Ramaprasad ,  William Elton Burky ,  Li Ma ,  Michael David Achenbach ,  Nicholas Andrew Plante ,  Yasuo Ishii

IPC: G06F9/38

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

公开(公告)号：US11907723B2

公开(公告)日：2024-02-20

申请号：US17699326

申请日：2022-03-21

Applicant: Arm Limited

Inventor： Nicholas Andrew Plante ,  Joseph Michael Pusdesris ,  Jungsoo Kim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/30029 ,  G06F9/30079 ,  G06F9/30181

Abstract: A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result.