公开(公告)号：US20160378682A1

公开(公告)日：2016-12-29

申请号：US14747980

申请日：2015-06-23

Applicant: Avanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Mike Mantor

IPC: G06F12/10 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

Abstract translation: 处理器在处理器的高速缓存中维护指示高速缓存未命中流的访问日志。 响应于高速缓存的高速缓存未命中的至少一个子集中的每一个，处理器在访问日志中记录相应的条目，指示导致相应的未命中的存储器访问请求的物理存储器地址。 此外，处理器维护地址转换日志，其指示物理存储器地址与虚拟存储器地址的映射。 响应于将虚拟地址转换为物理地址的地址转换（例如，寻路步行），处理器在地址转换日志的条目处存储物理地址与对应的虚拟地址的映射。 处理器执行的软件可以使用两个日志进行内存管理。

公开(公告)号：US11288205B2

公开(公告)日：2022-03-29

申请号：US14747980

申请日：2015-06-23

Applicant: Avanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Mike Mantor

IPC: G06F12/1027 ,  G06F12/0893

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US20160378674A1

公开(公告)日：2016-12-29

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F12/1081 ,  G06F15/163 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/251

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

Abstract translation: 处理器对处理器的异构处理单元使用相同的虚拟地址空间。 处理器对不同类型的处理单元（例如CPU和GPU）采用不同的页表，其中存储器管理单元使用每组页表来将虚拟地址空间的虚拟地址转换为存储器模块的相应物理地址 与处理器相关联。 随着数据在内存模块之间迁移，可以更新页表中的物理地址，以反映每个处理单元的数据的物理位置。

公开(公告)号：US11100004B2

公开(公告)日：2021-08-24

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/1009

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.