公开(公告)号：US20240134805A1

公开(公告)日：2024-04-25

申请号：US17970122

申请日：2022-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Naijie Li ,  Dong Hui Liu ,  Jing Lu ,  Peng Hui Jiang ,  Xiao Yan Tang ,  Bao Zhang ,  Yong Yin ,  Jun Su ,  Jia Yu

IPC: G06F12/1027 ,  G06N20/00

CPC classification number: G06F12/1027 ,  G06N20/00 ,  G06F2212/684

Abstract: A method, including: identifying static application features of an application; identifying resource access features of the application; labeling a translation lookaside buffer (TLB) miss threshold of a runtime feature of the application; determining utilization of larger pages during the runtime based on the TLB miss threshold; and setting the TLB miss threshold based on the determined utilization of the larger pages.

公开(公告)号：US20190171396A1

公开(公告)日：2019-06-06

申请号：US16188950

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/0888

CPC classification number: G06F3/0673 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0665 ,  G06F9/50 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/0888 ,  G06F12/1009 ,  G06F2212/60 ,  G06F2212/684

Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

公开(公告)号：US20180341599A1

公开(公告)日：2018-11-29

申请号：US16054772

申请日：2018-08-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin J. Ash ,  Matthew G. Borlick ,  Lokesh M. Gupta ,  Will A. Wright

IPC: G06F12/128 ,  G06F12/123 ,  G06F12/122

CPC classification number: G06F12/128 ,  G06F12/122 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/684

Abstract: Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

公开(公告)号：US10083126B2

公开(公告)日：2018-09-25

申请号：US15370570

申请日：2016-12-06

Applicant: ARM Limited

Inventor： Richard F Bryant ,  Max John Batley ,  Lilian Atieno Hutchins ,  Sujat Jamil

IPC: G06F12/12 ,  G06F12/10 ,  G06F12/1036

CPC classification number: G06F12/12 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/652 ,  G06F2212/681 ,  G06F2212/683 ,  G06F2212/684

Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data. A record of the candidate entries in then maintained, and, once the portion of the new data required for conflict detection is available, the conflict detection circuitry then performs a final stage detection operation to determine whether any of the candidate entries do contain data that conflicts with the new data. Any entries identified by the final stage detection operation as containing data that conflicts with the new data are then invalidated. This provides a particularly efficient mechanism for avoiding conflicting entries in a storage structure.

公开(公告)号：US10078588B2

公开(公告)日：2018-09-18

申请号：US15081379

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/657 ,  G06F2212/683 ,  G06F2212/684 ,  Y02D10/13

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.

公开(公告)号：US20180217930A1

公开(公告)日：2018-08-02

申请号：US15420667

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/0808 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/128 ,  G06F2212/401 ,  G06F2212/621 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：US20180157598A1

公开(公告)日：2018-06-07

申请号：US15369819

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： CHUNG-LUN CHAN ,  RAMON MATAS

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

Abstract: Methods, systems, and apparatuses relating to sharing translation lookaside buffer entries are described. In one embodiment, a processor includes one or more cores to execute a plurality of threads, a translation lookaside buffer comprising a plurality of entries, each entry comprising a virtual address to physical address translation and a plurality of bit positions, and each set bit of the plurality of bit positions in each entry indicating that the virtual address to physical address translation is valid for a respective thread of the plurality of threads, and a memory management circuit to clear all set bits for a thread by asserting a reset command to a respective reset port of the translation lookaside buffer for the thread, wherein the translation lookaside buffer comprises a separate reset port for each of the plurality of threads.

公开(公告)号：US20180113811A1

公开(公告)日：2018-04-26

申请号：US15332841

申请日：2016-10-24

Applicant: INTEL CORPORATION

Inventor： Bin Xing

IPC: G06F12/1009 ,  G06F12/128

CPC classification number: G06F12/1009 ,  G06F12/08 ,  G06F12/109 ,  G06F12/128 ,  G06F12/145 ,  G06F21/00 ,  G06F2212/1052 ,  G06F2212/657 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: An example system that includes a processor and a memory device. The processor may include multiple execution units to execute instructions and a memory device coupled to the processor. The memory device stores the instructions in an unprotected region and a protected region. The processor may determine that a first exception occurred while executing a first set of instructions for an application stored in a secured page of the protected region. The processor may invoke a first subroutine to forward exception context for the first exception to a second subroutine, where the first subroutine is stored in the protected region and the second subroutine is stored in the unprotected region. The processor may invoke, by the second subroutine, a third subroutine to execute a second set of instructions associated with the exception context for the first exception.

公开(公告)号：US20180089102A1

公开(公告)日：2018-03-29

申请号：US15824613

申请日：2017-11-28

Applicant: MIPS Tech, LLC

Inventor： Ranjit J. Rozario ,  Sanjay Patel

IPC: G06F12/1027 ,  G06F12/1045 ,  G06F12/1009 ,  G06F12/0844

CPC classification number: G06F12/1027 ,  G06F12/0844 ,  G06F12/1009 ,  G06F12/1054 ,  G06F2212/652 ,  G06F2212/684 ,  Y02D10/13

Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

公开(公告)号：US09870322B2

公开(公告)日：2018-01-16

申请号：US14939063

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

IPC: G06F12/10 ,  G06F9/50 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/1009

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/656 ,  G06F2212/68 ,  G06F2212/684

Abstract: In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into one or more partitions, including at least a first partition, and providing each partition for storage as individual stored objects in an OSD system. A processor adds a first entry in a page table, the first entry representing the first partition without an indication of a physical address. A memory management unit (MMU) of the OSD system receives a first request of the first partition. Responsive to receiving the first request of the first partition, a MMU identifies that the first entry of the page table represents the first partition. A MMU obtains a physical address of the first partition from one of a hardware component and a firmware component.