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公开(公告)号：US20200177833A1
公开(公告)日：2020-06-04
申请号：US16783492
申请日：2020-02-06
Inventor： Allen W. Hairston
IPC: H04N5/378 , H01L27/146 , G05F3/20 , G11C11/417
Abstract: Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.
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公开(公告)号：US20240365025A1
公开(公告)日：2024-10-31
申请号：US18139573
申请日：2023-04-26
Inventor： Allen W. Hairston , Thomas E. Collins
IPC: H04N25/78 , H04N25/707
CPC classification number: H04N25/78 , H04N25/707
Abstract: A neuromorphic focal plane array ROIC device for temporal and spatial synchronous and asynchronous image event processing comprising a plurality of pixels, each pixel comprising an input section comprising a Sample and Hold (SH) component; a low offset buffer/comparator section comprising a Switched Capacitor Filter (SCF); and a digital event output section comprising an analog pixel bus whereby temporal and spatial image data are synchronously and asynchronously processed.
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公开(公告)号：US11288461B2
公开(公告)日：2022-03-29
申请号：US16633223
申请日：2017-07-27
Inventor： Allen W. Hairston
Abstract: A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.
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公开(公告)号：US11558574B2
公开(公告)日：2023-01-17
申请号：US17120782
申请日：2020-12-14
Inventor： Allen W. Hairston , Thomas E. Collins, III
IPC: H04N5/365 , H04N5/3745 , H04N5/378 , H04N5/33 , H04N5/347
Abstract: A system for providing high resolution image output for pilotage and two color operation for threat detection is disclosed. The system comprises a focal plane array comprising a plurality of pixels arranged into groups of equal numbers, wherein each pixel comprises at least two detectors for receiving electromagnetic energy and a readout integrated circuit.
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Patent Agency Ranking
公开(公告)号：US20210250536A1
公开(公告)日：2021-08-12
申请号：US16787741
申请日：2020-02-11
Inventor： Thomas E. Collins, III , Dimitre P. Dimitrov , Allen W. Hairston
Abstract: Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).
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公开(公告)号：US20190356875A1
公开(公告)日：2019-11-21
申请号：US15985237
申请日：2018-05-21
Inventor： Allen W. Hairston , Daniel P. Lacroix
IPC: H04N5/378 , H04N5/33 , H01L27/146 , H04N5/369
Abstract: Methods and systems for enabling an approximation of true snapshot integration by lowering total power requirements, total detector bias current, integrated charge per detector and detector impedance while allowing for higher ROIC input noise through the use of microbolometer photodetectors, super-pixels, and techniques for their use are herein provided.
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公开(公告)号：US11523083B2
公开(公告)日：2022-12-06
申请号：US16787741
申请日：2020-02-11
Inventor： Thomas E. Collins, III , Dimitre P Dimitrov , Allen W. Hairston
Abstract: Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).
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公开(公告)号：US20220191408A1
公开(公告)日：2022-06-16
申请号：US17120782
申请日：2020-12-14
Inventor： Allen W. Hairston , Thomas E. Collins III
Abstract: A system for providing high resolution image output for pilotage and two color operation for threat detection, the system comprising a focal plane array, the focal plane array comprising: a plurality of pixels, wherein the pixels are arranged into groups of equal numbers of pixels, each pixel comprising: at least two detectors configured to receive electromagnetic energy; and a readout integrated circuit comprising an analog portion and a digital portion, which combine to form a current to frequency conversion circuit configured to convert current received from one of the at least two detectors into a pulse train, and a counter in operative communication with the frequency conversion circuit configured to count pulses in the pulse train during an integration time, wherein each detector from each of the pixels in a group of pixels is configured such that it can be connected to or disconnected from at least one detector from each adjacent pixel in a row or column from the same said group of pixels, and wherein each group of pixels is configured such that an output from detectors connected to one another is directed through the readout integrated circuit of a single pixel from the group of pixels.
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公开(公告)号：US11350054B2
公开(公告)日：2022-05-31
申请号：US16783492
申请日：2020-02-06
Inventor： Allen W. Hairston
IPC: G01J5/00 , H04N5/378 , G11C11/417 , G05F3/20 , H01L27/146
Abstract: Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.
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