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公开(公告)号：US20170026004A1
公开(公告)日：2017-01-26
申请号：US15216156
申请日：2016-07-21
Inventor： Mark E. Stuenkel , Kevin W. Sliech
CPC classification number: H03F1/3211 , H03F3/45475 , H03F3/45977 , H03F3/72 , H03F2203/45534 , H03F2203/45562
Abstract: A feedback amplifier having an improved feedback network including two cross coupled switches that isolate the amplifier from extraneous undesired electrical signals present in a system or network when the amplifier is turned off (i.e., in an off-state). The cross coupled switches interconnect two feedback paths of a feedback network to enable out-of-phase differential signals to be summed and effectively canceled. Further, the feedback amplifier provides on-stage advantages to enable different amplifier characteristics and parameter to be selectively engaged by turning on or turning off certain feedback networks.
Abstract translation: 反馈放大器具有改进的反馈网络，包括两个交叉耦合的开关，当放大器被关闭（即，处于关闭状态）时，放大器与存在于系统或网络中的外来不需要的电信号隔离。 交叉耦合开关互连反馈网络的两个反馈路径，以使异相差分信号相加和有效地消除。 此外，反馈放大器提供了阶段上的优点，以通过打开或关闭某些反馈网络来使得能够选择性地接合不同的放大器特性和参数。
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公开(公告)号：US11057067B1
公开(公告)日：2021-07-06
申请号：US16846824
申请日：2020-04-13
Inventor： Mark D. Hickle , Robert W. Sepanek , Mark E. Stuenkel
Abstract: Techniques are disclosed for self-interference signal cancellation. A hybrid self-interference cancellation (SIC) circuit is configured to be operatively coupled to a transmitter and a receiver, and includes a tunable time domain filter in series with a tunable frequency domain filter. The tunable time domain filter is configured to generate a time-domain multipath cancellation signal based on a first radio signal transmitted by the transmitter at a first frequency while the receiver is receiving a second radio signal at a second frequency. The first and second frequencies can be the same or different and have similar or different power levels at the antennas. The tunable frequency domain filter, which is in series with the tunable time domain filter, is configured to generate a frequency-domain cancellation signal based on the first radio signal while the receiver is receiving the second radio signal.
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公开(公告)号：US09859849B2
公开(公告)日：2018-01-02
申请号：US15216156
申请日：2016-07-21
Inventor： Mark E. Stuenkel , Kevin W. Sliech
CPC classification number: H03F1/3211 , H03F3/45475 , H03F3/45977 , H03F3/72 , H03F2203/45534 , H03F2203/45562
Abstract: A feedback amplifier having an improved feedback network including two cross coupled switches that isolate the amplifier from extraneous undesired electrical signals present in a system or network when the amplifier is turned off (i.e., in an off-state). The cross coupled switches interconnect two feedback paths of a feedback network to enable out-of-phase differential signals to be summed and effectively canceled. Further, the feedback amplifier provides on-stage advantages to enable different amplifier characteristics and parameter to be selectively engaged by turning on or turning off certain feedback networks.
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Patent Agency Ranking
公开(公告)号：US11005482B1
公开(公告)日：2021-05-11
申请号：US16740103
申请日：2020-01-10
Inventor： Mark E. Stuenkel , Mark D. Hickle
Abstract: Techniques are disclosed for phase detection in a phase-locked loop (PLL) control system, such as a millimeter-wave PLL. A PLL control system includes a voltage-controlled oscillator (VCO) circuit and a sub-sampling phase detector (SSPD). The VCO circuit is configured to generate an oscillating VCO output voltage based at least in part on an error signal generated by the SSPD. The error signal is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage. The SSPD includes a switched emitter-follower (SEF) sampling network, also referred to in this disclosure as an SEF circuit. In contrast to existing CMOS-based techniques, the SEF sampling network allows the SSPD to operate up to higher frequencies, for example, greater than 100 GHz, than possible using a CMOS sampler, and is also compatible with BiCMOS processes, which generally do not have access to advanced small-geometry CMOS.
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公开(公告)号：US10097199B1
公开(公告)日：2018-10-09
申请号：US15893895
申请日：2018-02-12
Inventor： Lawrence J. Kushner , Mark E. Stuenkel , Steven E. Turner
Abstract: A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.
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公开(公告)号：US11139847B2
公开(公告)日：2021-10-05
申请号：US16738475
申请日：2020-01-09
Inventor： Mark E. Stuenkel , Mark D. Hickle
Abstract: A radio frequency (RF) filter includes a signal conditioning circuit and a bandstop filter. The signal conditioning circuit receives a broadband RF signal that includes both a jamming signal at a jamming frequency and a signal of interest and generates a plurality of clock signals. Each of the plurality of clock signals has a substantially same frequency as the jamming frequency, but a different phase shift. The bandstop filter receives the RF signal and the plurality of clock signals. The bandstop filter attenuates signals within a bandstop centered at the frequency of the plurality of clock signals. A self-tuning N-path filter is provided.
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公开(公告)号：US20210218429A1
公开(公告)日：2021-07-15
申请号：US16738475
申请日：2020-01-09
Inventor： Mark E. Stuenkel , Mark D. Hickle
Abstract: A radio frequency (RF) filter includes a signal conditioning circuit and a bandstop filter. The signal conditioning circuit receives a broadband RF signal that includes both a jamming signal at a jamming frequency and a signal of interest and generates a plurality of clock signals. Each of the plurality of clock signals has a substantially same frequency as the jamming frequency, but a different phase shift. The bandstop filter receives the RF signal and the plurality of clock signals. The bandstop filter attenuates signals within a bandstop centered at the frequency of the plurality of clock signals. A self-tuning N-path filter is provided.
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公开(公告)号：US10056891B1
公开(公告)日：2018-08-21
申请号：US15908381
申请日：2018-02-28
Inventor： Mark E. Stuenkel , Lawrence J. Kushner
CPC classification number: H03K5/1565 , H03K5/159 , H03M1/121 , H03M1/662
Abstract: A duty cycle adjustment circuit includes: a delay circuit to delay an input clock signal to produce a delayed clock signal having a rising edge partially overlapping the rising edge of the input clock signal, the input clock signal oscillating between first and second values about a midpoint value; a blender circuit to blend the input clock signal and the delayed clock signal to produce a blended clock signal; a buffer circuit to buffer the input clock signal for an amount of time comparable to the blender circuit, to produce a buffered clock signal; and a combiner circuit to combine the buffered and the blended clock signals to produce an output clock signal that transitions to or remains at the first value when both the buffered and blended clock signals are on the first value side of the midpoint value, and otherwise transitions to or remains at the second value.
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