公开(公告)号：US20160308536A1

公开(公告)日：2016-10-20

申请号：US15099753

申请日：2016-04-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： JOSEPH D. CALI ,  CURTIS M. GRENS ,  LAWRENCE J. KUSHNER ,  STEVEN E. TURNER

IPC: H03K21/02 ,  H03K21/38 ,  H03L7/197

CPC classification number: H03K21/026 ,  G06F1/08 ,  G06F7/68 ,  H03K21/00 ,  H03K21/10 ,  H03K21/38 ,  H03K21/40 ,  H03K23/00 ,  H03K23/40 ,  H03K23/58 ,  H03K23/64 ,  H03K23/68 ,  H03L7/1974

Abstract: Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

Abstract translation: 可以使用分频器技术来解决两个问题：如果模数控制在分频周期完成之前变化，并且当由于边界穿越而发生不正确的划分时（例如，功率2 在分数N PLL应用中的边界交叉）。 在一个实施例中，提供了一种分频器，其包括可操作地耦合以执行输入频率划分的多个触发器，并且被配置为产生模数输出并接收先前小区的分频时钟信号。 至少部分地基于施加到附加触发器的数据输入端的跳过控制信号，另外的触发器选择性地将时钟从先前级的模数输出或分频时钟中的一个计时，并进一步被配置为 有选择地将多个触发器复位到将导致正确分频比的状态。

公开(公告)号：US20160226502A1

公开(公告)日：2016-08-04

申请号：US15099757

申请日：2016-04-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： JOSEPH D. CALI ,  LAWRENCE J. KUSHNER

IPC: H03L7/197 ,  H03M3/00

CPC classification number: H03L7/1974 ,  H03L7/1976 ,  H03M7/3033

Abstract: Techniques are disclosed for managing the timing between two asynchronous clocks. The techniques are particularly well-suited for synchronizing the reference clock with the divided clock in a phase coherent DSM PLL application, but can be more broadly applied to any application that includes a need for synchronizing a data bus across a clock boundary. In one example embodiment, the techniques are implemented in a retime word circuit operatively coupled between a DSM and the divide-by-N integer divider of a PLL application. The retime word circuit receives the divide word from the DSM and generates a retimed divide word that can be applied to the divider. The retime word circuit maintains the reference clock frequency throughput, and forces the divide word seen by the divider to change only at end of a given divide cycle.

Abstract translation: 公开了用于管理两个异步时钟之间的定时的技术。 这些技术特别适合于在相位相干DSM PLL应用中将参考时钟与分频时钟同步，但是可以更广泛地应用于包括在时钟边界上同步数据总线的任何应用。 在一个示例实施例中，这些技术在可操作地耦合在DSM和PLL应用的除以N整数除法器之间的复现字电路中实现。 复位字电路从DSM接收除法字，并产生可应用于除法器的重新定时除法字。 复位字电路保持参考时钟频率吞吐量，并且迫使除法器看到的除法字只在给定的分频周期结束时改变。