POWER AND SYSTEM MANAGEMENT INFORMATION VISIBILITY
    1.
    发明申请
    POWER AND SYSTEM MANAGEMENT INFORMATION VISIBILITY 审中-公开
    电力和系统管理信息可视性

    公开(公告)号:US20140223217A1

    公开(公告)日:2014-08-07

    申请号:US13950725

    申请日:2013-07-25

    Abstract: Aspects of power and system management information visibility are described. In various embodiments, a system parameter of a system is measured. The system parameter may include one or more parameters such as system voltages, temperatures, options, or conditions of the system. The system parameter may be evaluated by a power manager processor. The evaluation may determine operating settings for one or more elements of the system. Based on the evaluation, one or more operating parameters for elements of the system may be set, in advance of powering up the system elements. After the operating parameters have been set, system elements may be released to start or boot based on the operating parameters. In this manner, one or more elements of the system may power on in a more flexible and deliberate manner, taking the current operating environment of the system into consideration.

    Abstract translation: 描述了电力和系统管理信息可视性的方面。 在各种实施例中,测量系统的系统参数。 系统参数可以包括一个或多个参数,例如系统电压,温度,选项或系统的条件。 系统参数可以由功率管理器处理器来评估。 评估可以确定系统的一个或多个元件的操作设置。 基于该评估,可以在对系统元件供电之前设置用于系统的元件的一个或多个操作参数。 操作参数设置完成后,可根据操作参数释放系统元件启动或启动。 以这种方式,考虑到系统的当前操作环境,系统的一个或多个元件可以以更灵活和故意的方式上电。

    CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES
    4.
    发明申请
    CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES 有权
    时钟交叉串行接口,直接锁定和响应代码

    公开(公告)号:US20140223031A1

    公开(公告)日:2014-08-07

    申请号:US13950713

    申请日:2013-07-25

    Abstract: Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.

    Abstract translation: 描述串行接口的时钟域,串行接口上​​的直接锁存和响应代码的方面。 在各种实施例中,识别通过串行接口接收的数据通信命令,并且解析通过串行接口接收的地址以访问寄存器组。 在写操作中,根据地址是否落在寄存器组的直接锁存地址范围内,数据可以被直接锁存到寄存器组的直接锁存寄存器中或者先进先出寄存器。 对于读和写操作,可以参考串行接口的状态寄存器来识别或减轻错误状况,并且可以依赖等待时间来考虑时钟域穿越。 在每次读取和写入操作之后,可以传送包括状态指示器的响应代码。

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