公开(公告)号：US08878707B1

公开(公告)日：2014-11-04

申请号：US13967819

申请日：2013-08-15

Applicant: Broadcom Corporation

Inventor： Tao Wang ,  Chun-Ying Chen ,  Massimo Brandolini ,  Wei-Te Chou

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0836 ,  H03M1/1245 ,  H03M1/164

Abstract: A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.

Abstract translation: 系统包括第一存储元件，用于存储用于无SHA阶段的第一采样通道的输入信号。 第一开关与第一存储元件连接，第一开关用于控制第一存储元件何时存储用于在第一采样通道上采样的输入信号。 第二开关与第一开关串联连接，第二开关用于控制用于对存储在第一采样通道的第一存储元件上的输入信号进行采样的实例。

公开(公告)号：US09154150B1

公开(公告)日：2015-10-06

申请号：US14336916

申请日：2014-07-21

Applicant: Broadcom Corporation

Inventor： Jiangfeng Wu ,  Wei-Te Chou ,  Rong Wu

IPC: H03M1/12

CPC classification number: H03M1/124 ,  H03M1/1215 ,  H03M1/144

Abstract: An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N−2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N−2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.

Abstract translation: 在多个转换阶段利用电容器阵列的模/数转换器（ADC）和跨多个通道的放大器共享。 在各种实施例中，ADC包括N个通道，每个通道包括电容器阵列。 耦合到每个电容器阵列的多个开关在对应于N个转换级的N个时钟相位期间选择性地重新分配采样的电荷，转换级包括对模拟输入信号执行的采样级，至少一个量化级和N-2​​倍数字 模拟转换（MDAC）级，用于产生残余电压。 MDAC级利用N通道共享的多个N-2放大器。 在操作中，每个放大器可以以交错方式使用，以在给定的时钟相位期间支持ADC的一条通道的MDAC级。 类似地，可以利用一个或多个通道的比较器在N个时钟相位期间执行多个量化级。