Abstract:
An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N−2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N−2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.
Abstract:
A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.
Abstract:
An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures.
Abstract:
A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.