Interleaved multiple-stage capacitor and amplifier sharing in an ADC
    1.
    发明授权
    Interleaved multiple-stage capacitor and amplifier sharing in an ADC 有权
    在ADC中交错多级电容和放大器共享

    公开(公告)号:US09154150B1

    公开(公告)日:2015-10-06

    申请号:US14336916

    申请日:2014-07-21

    CPC classification number: H03M1/124 H03M1/1215 H03M1/144

    Abstract: An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N−2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N−2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.

    Abstract translation: 在多个转换阶段利用电容器阵列的模/数转换器(ADC)和跨多个通道的放大器共享。 在各种实施例中,ADC包括N个通道,每个通道包括电容器阵列。 耦合到每个电容器阵列的多个开关在对应于N个转换级的N个时钟相位期间选择性地重新分配采样的电荷,转换级包括对模拟输入信号执行的采样级,至少一个量化级和N-2​​倍数字 模拟转换(MDAC)级,用于产生残余电压。 MDAC级利用N通道共享的多个N-2放大器。 在操作中,每个放大器可以以交错方式使用,以在给定的时钟相位期间支持ADC的一条通道的MDAC级。 类似地,可以利用一个或多个通道的比较器在N个时钟相位期间执行多个量化级。

    Dynamic tracking nonlinearity correction
    3.
    发明授权
    Dynamic tracking nonlinearity correction 有权
    动态跟踪非线性校正

    公开(公告)号:US09559713B1

    公开(公告)日:2017-01-31

    申请号:US15057609

    申请日:2016-03-01

    Inventor: Rong Wu Tianwei Li

    CPC classification number: H03M1/124 H03M1/1038

    Abstract: An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures.

    Abstract translation: 模拟 - 数字转换器(ADC)用于动态跟踪非线性校正。 该校正采用模拟采样技术通过在采样时刻测量由模拟输入信号进行模数转换的模拟输入信号产生的微分电流来确定信号导数。 与数字方法相比,模拟导数采样技术以较少的复杂度实现了功耗的显着降低,HD3,SDFR和IM3措施的强劲改进。

    System and Method for Integration of Hybrid Pipeline
    4.
    发明申请
    System and Method for Integration of Hybrid Pipeline 有权
    混合管道整合系统与方法

    公开(公告)号:US20150009059A1

    公开(公告)日:2015-01-08

    申请号:US14021735

    申请日:2013-09-09

    Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

    Abstract translation: 系统包括作为处理输入信号的第一级的流水线模数转换器和用于处理输入信号的逐次逼近寄存器(SAR)模数转换器作为第二级。 SAR模数转换器包括功率调整元件,用于调整SAR模数转换器的参考电压,以匹配流水线模数转换器的满量程电压。

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