公开(公告)号：US20160294404A1

公开(公告)日：2016-10-06

申请号：US14699866

申请日：2015-04-29

Applicant: Broadcom Corporation

Inventor： Jiangfeng Wu

IPC: H03M1/06 ,  H04L1/00 ,  H04B1/69 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/0609 ,  H03M1/0641 ,  H03M1/121 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/462 ,  H04L1/0071

Abstract: Methods, systems, and apparatuses, including electrical circuits, are described for spread spectrum ADC noise reduction. An analog-to-digital converter may include an analog modulator to modulate an input analog signal according to a pseudo-noise sequence. An ADC core may convert the modulated analog input signal to a digital signal representation thereof. The digital signal may be demodulated using the pseudo-noise sequence to generate a noise-spread signal with reduced noise spectral density. The analog modulator and digital demodulator may also be configured in an analog-to-digital converter that includes a comparator and successive approximation register (SAR) logic, rather than an ADC core, in a SAR implementation. Multi-lane, interleaved analog-to-digital conversion circuits are also described using the inventive techniques. Analog-to-digital converters including DC offset components and methods performed according to the inventive techniques are also described.

Abstract translation: 描述了用于扩频ADC噪声降低的方法，系统和装置，包括电路。 模拟 - 数字转换器可以包括模拟调制器，以根据伪噪声序列来调制输入模拟信号。 ADC内核可以将调制的模拟输入信号转换成其数字信号表示。 可以使用伪噪声序列来解调数字信号，以产生具有降低的噪声频谱密度的噪声扩展信号。 模拟调制器和数字解调器也可以配置在模数转换器中，该转换器在SAR实现中包括比较器和逐次逼近寄存器（SAR）逻辑，而不是ADC核心。 还使用本发明的技术来描述多通道交错模数转换电路。 还描述了包括DC偏移分量和根据本发明技术执行的方法的模数转换器。

公开(公告)号：US09455733B1

公开(公告)日：2016-09-27

申请号：US14699866

申请日：2015-04-29

Applicant: Broadcom Corporation

Inventor： Jiangfeng Wu

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H04B1/69 ,  H04L1/00

CPC classification number: H03M1/0609 ,  H03M1/0641 ,  H03M1/121 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/462 ,  H04L1/0071

Abstract: Methods, systems, and apparatuses, including electrical circuits, are described for spread spectrum ADC noise reduction. An analog-to-digital converter may include an analog modulator to modulate an input analog signal according to a pseudo-noise sequence. An ADC core may convert the modulated analog input signal to a digital signal representation thereof. The digital signal may be demodulated using the pseudo-noise sequence to generate a noise-spread signal with reduced noise spectral density. The analog modulator and digital demodulator may also be configured in an analog-to-digital converter that includes a comparator and successive approximation register (SAR) logic, rather than an ADC core, in a SAR implementation. Multi-lane, interleaved analog-to-digital conversion circuits are also described using the inventive techniques. Analog-to-digital converters including DC offset components and methods performed according to the inventive techniques are also described.

Abstract translation: 描述了用于扩频ADC噪声降低的方法，系统和装置，包括电路。 模拟 - 数字转换器可以包括模拟调制器，以根据伪噪声序列来调制输入模拟信号。 ADC内核可以将调制的模拟输入信号转换成其数字信号表示。 可以使用伪噪声序列来解调数字信号，以产生具有降低的噪声频谱密度的噪声扩展信号。 模拟调制器和数字解调器也可以配置在模数转换器中，该转换器在SAR实现中包括比较器和逐次逼近寄存器（SAR）逻辑，而不是ADC核心。 还使用本发明的技术来描述多通道交错模数转换电路。 还描述了包括DC偏移分量和根据本发明技术执行的方法的模数转换器。

公开(公告)号：US20140286462A1

公开(公告)日：2014-09-25

申请号：US13863873

申请日：2013-04-16

Applicant: BROADCOM CORPORATION

Inventor： Jiangfeng Wu ,  John Lock Creigh

IPC: H04B1/10

CPC classification number: H04B1/1027 ,  H04L27/01

Abstract: Disclosed are various embodiments for reducing the amount of electromagnetic interference (EMI) that may be present in a received signal. A frequency component for the received component is generated. An EMI frequency, an EMI phase, and an EMI amplitude present in the frequency component are tracked. Cancelling data is generated responsive to the EMI frequency, the EMI phase, and the EMI amplitude present in the frequency component.

Abstract translation: 公开了用于减少可能存在于接收信号中的电磁干扰（EMI）量的各种实施例。 生成接收到的分量的频率分量。 跟踪频率分量中存在的EMI频率，EMI相位和EMI振幅。 根据EMI频率，EMI相位和频率分量中存在的EMI振幅来产生取消数据。

公开(公告)号：US20140184339A1

公开(公告)日：2014-07-03

申请号：US13768713

申请日：2013-02-15

Applicant: BROADCOM CORPORATION

Inventor： Ramon GOMEZ ,  Massmo Brandolini ,  Jiangfeng Wu ,  Kevin Lee Miller ,  Hans Eberhart ,  Tianwei Li

IPC: H03F3/21 ,  H03F3/19 ,  H03M1/66

CPC classification number: H03F3/21 ,  H03F1/0277 ,  H03F1/22 ,  H03F3/19 ,  H03F3/193 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/516 ,  H03F2203/45496 ,  H03F2203/45656 ,  H03F2203/45731 ,  H03M1/66

Abstract: Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fail. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

Abstract translation: 提供高功率发射机输出级设计。 在一个实施例中，输入信号的概率密度函数（PDF）被划分为多个区域，并且根据其中它们失败的PDF的区域来处理输入信号的采样。 PDF可以在对应于在预定幅度范围内的输入信号的样本的内部区域和对应于在预定幅度范围之外的输入信号的采样的外部区域之间划分。 落入内部区域的输入信号的样本由A类偏置放大器处理，落在外部区域的输入信号的采样由B类偏置放大器处理。 根据实施例的输出级设计可以被实现为功率放大器或功率数模转换器（DAC）。

公开(公告)号：US08730073B1

公开(公告)日：2014-05-20

申请号：US13738557

申请日：2013-01-10

Applicant: Broadcom Corporation

Inventor： Tao Wang ,  Chun-Ying Chen ,  Jiangfeng Wu

IPC: H03M1/00

CPC classification number: H03M1/1215 ,  H03M1/167

Abstract: A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Abstract translation: 通过流水线模数转换器（ADC）对模拟信号进行数字化的方法可以包括将样本子级，量子化级和放大级分别流水线到ADC通道。 在多个流水线阶段的第一阶段中，可以将时钟相位分配给ADC通道，包括采样时钟相位，量化时钟相位和放大时钟相位，使得量化时钟相位与采样时钟相位不重叠， 放大时钟相位。 可以通过为多个ADC通道的子级产生多个参考时钟相位并且将采样时钟相位，量化时钟相位和放大时钟相位的分配交织到参考时钟相位中，从而促进非重叠特征 多条车道。

公开(公告)号：US09614662B2

公开(公告)日：2017-04-04

申请号：US14692361

申请日：2015-04-21

Applicant: Broadcom Corporation

Inventor： Frank Van der Goes ,  Jiangfeng Wu ,  David Garrett

IPC: H03K9/00 ,  H04L7/033 ,  H04B1/16 ,  H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0331 ,  H04B1/001 ,  H04B1/16 ,  H04B7/0837 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/0334 ,  H04L7/0337

Abstract: In some aspects, the disclosure is directed to methods and systems of a multi-input receiver. In one or more embodiments, a receiver receives a plurality of signals each via a respective one of a plurality of wireless channels. In one or more embodiments, a processing stage of the receiver combines the received plurality of signals into a combined signal for input to an analog-to-digital converter (ADC) of the receiver. In one or more embodiments, the ADC generates, at a predetermined sampling frequency, samples of the combined signal. In one or more embodiments, the receiver recovers from the generated samples at least one signal component corresponding to at least one of the plurality of signals.

公开(公告)号：US09214949B1

公开(公告)日：2015-12-15

申请号：US14583907

申请日：2014-12-29

Applicant: BROADCOM CORPORATION

Inventor： Jiangfeng Wu ,  Tianwei Li

IPC: H03M1/34 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0624 ,  H02M3/07 ,  H03M1/12

Abstract: An Analog to Digital Converter (ADC) includes an ADC core, a first switched capacitor voltage regulator, and a second switched capacitor voltage regulator. The ADC core includes a plurality of digital components that sample an incoming signal based on an ADC clock, a first voltage, and a first ground and a plurality of analog components configured to operate using a second voltage and a second ground. The first switched capacitor voltage regulator produces the first voltage and the first ground for the plurality of digital components using a supply voltage, a supply ground, and the ADC clock. The second switched capacitor voltage regulator produces the second voltage and the second ground using the supply voltage, the supply ground, and the ADC clock. Switching of the first and second switched capacitor voltage regulators is performed using complementary and non-overlapping clocks having switching frequency that is based upon the ADC clock.

Abstract translation: 模数转换器（ADC）包括ADC内核，第一开关电容器电压调节器和第二开关电容器电压调节器。 ADC内核包括多个数字组件，其基于ADC时钟，第一电压以及第一地和多个被配置为使用第二电压和第二地进行操作的模拟组件对输入信号进行采样。 第一开关电容器电压调节器使用电源电压，电源地和ADC时钟产生用于多个数字组件的第一电压和第一接地。 第二个开关电容器电压调节器使用电源电压，电源地和ADC时钟产生第二个电压和第二个接地。 使用具有基于ADC时钟的开关频率的互补和非重叠时钟来执行第一和第二开关电容器稳压器的切换。

公开(公告)号：US09154150B1

公开(公告)日：2015-10-06

申请号：US14336916

申请日：2014-07-21

Applicant: Broadcom Corporation

Inventor： Jiangfeng Wu ,  Wei-Te Chou ,  Rong Wu

IPC: H03M1/12

CPC classification number: H03M1/124 ,  H03M1/1215 ,  H03M1/144

Abstract: An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N−2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N−2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.

Abstract translation: 在多个转换阶段利用电容器阵列的模/数转换器（ADC）和跨多个通道的放大器共享。 在各种实施例中，ADC包括N个通道，每个通道包括电容器阵列。 耦合到每个电容器阵列的多个开关在对应于N个转换级的N个时钟相位期间选择性地重新分配采样的电荷，转换级包括对模拟输入信号执行的采样级，至少一个量化级和N-2​​倍数字 模拟转换（MDAC）级，用于产生残余电压。 MDAC级利用N通道共享的多个N-2放大器。 在操作中，每个放大器可以以交错方式使用，以在给定的时钟相位期间支持ADC的一条通道的MDAC级。 类似地，可以利用一个或多个通道的比较器在N个时钟相位期间执行多个量化级。

公开(公告)号：US08912937B2

公开(公告)日：2014-12-16

申请号：US13768713

申请日：2013-02-15

Applicant: Broadcom Corporation

Inventor： Ramon Gomez ,  Massimo Brandolini ,  Jiangfeng Wu ,  Kevin Lee Miller ,  Hans Eberhart ,  Tianwei Li

IPC: H03M1/66 ,  H03F3/19 ,  H03F3/21

CPC classification number: H03F3/21 ,  H03F1/0277 ,  H03F1/22 ,  H03F3/19 ,  H03F3/193 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/516 ,  H03F2203/45496 ,  H03F2203/45656 ,  H03F2203/45731 ,  H03M1/66

Abstract: Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fall. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

Abstract translation: 提供高功率发射机输出级设计。 在一个实施例中，输入信号的概率密度函数（PDF）被划分为多个区域，并且根据它们所在的PDF的区域来处理输入信号的采样。 PDF可以在对应于在预定幅度范围内的输入信号的样本的内部区域和对应于在预定幅度范围之外的输入信号的采样的外部区域之间划分。 落入内部区域的输入信号的样本由A类偏置放大器处理，落在外部区域的输入信号的采样由B类偏置放大器处理。 根据实施例的输出级设计可以被实现为功率放大器或功率数模转换器（DAC）。

公开(公告)号：US20160285617A1

公开(公告)日：2016-09-29

申请号：US14692361

申请日：2015-04-21

Applicant: Broadcom Corporation

Inventor： Frank Van der Goes ,  Jiangfeng Wu ,  David Garrett

IPC: H04L7/033 ,  H04B1/16

CPC classification number: H04L7/0331 ,  H04B1/001 ,  H04B1/16 ,  H04B7/0837 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/0334 ,  H04L7/0337

Abstract: In some aspects, the disclosure is directed to methods and systems of a multi-input receiver. In one or more embodiments, a receiver receives a plurality of signals each via a respective one of a plurality of wireless channels. In one or more embodiments, a processing stage of the receiver combines the received plurality of signals into a combined signal for input to an analog-to-digital converter (ADC) of the receiver. In one or more embodiments, the ADC generates, at a predetermined sampling frequency, samples of the combined signal. In one or more embodiments, the receiver recovers from the generated samples at least one signal component corresponding to at least one of the plurality of signals.

Abstract translation: 在一些方面，本公开涉及多输入接收机的方法和系统。 在一个或多个实施例中，接收机经由多个无线信道中的相应一个接收多个信号。 在一个或多个实施例中，接收机的处理级将所接收的多个信号组合成用于输入到接收机的模数转换器（ADC）的组合信号。 在一个或多个实施例中，ADC以预定采样频率产生组合信号的采样。 在一个或多个实施例中，接收机从所生成的采样中恢复与多个信号中的至少一个对应的至少一个信号分量。