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公开(公告)号：US20060233291A1
公开(公告)日：2006-10-19
申请号：US11404502
申请日：2006-04-14
IPC分类号： H04L7/00
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second edge samples. The phase of the sampling clock signal is adjusted based, at least in part, on the first edge sample if the set of data samples matches a first data pattern and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.
摘要翻译： 在集成电路器件内的接收电路中，响应于采样时钟信号的转变对二进制输入信号进行采样以产生一组数据采样。 另外将二进制输入信号与第一和第二阈值电平进行比较以产生相应的第一和第二边缘采样。 至少部分地基于第一边缘采样来调整采样时钟信号的相位，如果该组数据样本与第一数据模式匹配，并且至少部分地基于第二边缘采样，如果数据集合 样本匹配第二个数据模式。
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公开(公告)号：US07433397B2
公开(公告)日：2008-10-07
申请号：US11404502
申请日：2006-04-14
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second edge samples. The phase of the sampling clock signal is adjusted based, at least in part, on the first edge sample if the set of data samples matches a first data pattern and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.
摘要翻译： 在集成电路器件内的接收电路中，响应于采样时钟信号的转变对二进制输入信号进行采样以产生一组数据采样。 另外将二进制输入信号与第一和第二阈值电平进行比较以产生相应的第一和第二边缘采样。 至少部分地基于第一边缘采样来调整采样时钟信号的相位，如果该组数据样本与第一数据模式匹配，并且至少部分地基于第二边缘采样，如果数据集合 样本匹配第二个数据模式。
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