公开(公告)号：US08634452B2

公开(公告)日：2014-01-21

申请号：US13491508

申请日：2012-06-07

申请人： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett, Jr. ,  Carl W. Werner

发明人： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett, Jr. ,  Carl W. Werner

IPC分类号： H04B17/00

CPC分类号： H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

摘要： An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.

摘要翻译： 集成电路装置包括：第一电路，用于接收与电输入信号的第一数据周期相关联的位，可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路，用于接收与第 电输入信号的第二周期，以产生关于与第二数据周期相关联的位的逻辑状态的判定。 均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰，并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰，该电路可操作以产生关于位的逻辑状态的判定 的电气输入信号。

公开(公告)号：US07715509B2

公开(公告)日：2010-05-11

申请号：US12403340

申请日：2009-03-12

申请人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C. C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno W. Garlepp

发明人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C. C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno W. Garlepp

IPC分类号： H04L7/00

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

公开(公告)号：US07715501B2

公开(公告)日：2010-05-11

申请号：US10966070

申请日：2004-10-18

申请人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C. C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno W. Garlepp

发明人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C. C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno W. Garlepp

IPC分类号： H04L27/06

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

摘要翻译： 用于接收经由电信号导体发送的信号的接收电路。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

公开(公告)号：US07706480B2

公开(公告)日：2010-04-27

申请号：US12508030

申请日：2009-07-23

申请人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C. C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno W. Garlepp

发明人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C. C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno W. Garlepp

IPC分类号： H04L27/06

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： An integrated circuit device having a receive circuit is disclosed. The receive circuit generates first and second sets of samples of incoming symbols during first and second time intervals, respectively. A select circuit selects, based at least in part on the first set of samples, at least one sample from the second set to be output as a received data value. The integrated circuit device further includes a transmit circuit to generate an output symbol during a third time interval. The output symbol has an amplitude based, at least in part, on a transmit data value for which an output symbol was generated during a time interval prior to the third time interval.

摘要翻译： 公开了一种具有接收电路的集成电路装置。 接收电路分别在第一和第二时间间隔期间产生输入符号的第一和第二组样本。 选择电路至少部分地基于第一组采样选择要作为接收数据值输出的来自第二组的至少一个采样。 集成电路装置还包括在第三时间间隔期间产生输出符号的发送电路。 输出符号至少部分地基于在第三时间间隔之前的时间间隔期间产生输出符号的发送数据值。

公开(公告)号：US20100020861A1

公开(公告)日：2010-01-28

申请号：US12558133

申请日：2009-09-11

申请人： Brian S. Leibowitz ,  Bruno W. Garlepp

发明人： Brian S. Leibowitz ,  Bruno W. Garlepp

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  G01R31/31709 ,  G01R31/31711 ,  H04J11/0023 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244 ,  H04L5/006 ,  H04L7/033 ,  H04L25/03146

摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

摘要翻译： 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。 一些实施例允许独立于采样定时来调整反馈定时以测量某些形式的相位未对准和抖动的影响。

公开(公告)号：US20090175326A1

公开(公告)日：2009-07-09

申请号：US12403340

申请日：2009-03-12

申请人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C.C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno w. Garlepp

发明人： Vladimir M. Stojanovic ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Anthony Bessios ,  Andrew C.C. Ho ,  Jason C. Wei ,  Grace Tsang ,  Bruno w. Garlepp

IPC分类号： H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

摘要翻译： 用于接收经由电信号导体发送的信号的接收电路。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

公开(公告)号：US07193467B2

公开(公告)日：2007-03-20

申请号：US10811922

申请日：2004-03-30

申请人： Bruno W. Garlepp ,  Andrew C. C. Ho

发明人： Bruno W. Garlepp ,  Andrew C. C. Ho

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45748 ,  H03F2203/45362 ,  H03F2203/45574 ,  H03F2203/45702

摘要： A differential amplifier and method of using same are disclosed. In one particular exemplary embodiment, the present invention may be realized as a circuit comprising a differential amplifier for receiving a differential input signal and generating a differential output signal, a comparator for generating an adjustment signal based at least in part upon the differential output signal, and a current controller for controlling current steering and at least one offset current in the differential amplifier based at least in part upon the adjustment signal and a current steering variable signal.

摘要翻译： 公开了一种差分放大器及其使用方法。 在一个特定的示例性实施例中，本发明可以被实现为包括用于接收差分输入信号并产生差分输出信号的差分放大器的电路，用于至少部分地基于差分输出信号产生调整信号的比较器， 以及电流控制器，用于至少部分地基于所述调整信号和当前转向可变信号来控制所述差分放大器中的电流转向和至少一个偏移电流。

公开(公告)号：US07084710B2

公开(公告)日：2006-08-01

申请号：US10998521

申请日：2004-11-29

申请人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

发明人： Yunteng Huang ,  Bruno W. Garlepp ,  David R. Welland

IPC分类号： H03L7/099

CPC分类号： H03L7/093 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06 ,  H03M7/3011 ,  H03M7/3028 ,  H03M7/3037

摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

摘要翻译： 示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。 用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。 复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。 每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

公开(公告)号：US06950956B2

公开(公告)日：2005-09-27

申请号：US10700655

申请日：2003-11-03

申请人： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

发明人： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC分类号： G06F1/10 ,  G06F13/42 ,  G06F1/12

CPC分类号： G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

摘要： An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

摘要翻译： 集成电路装置包括接收器，寄存器和时钟电路。 接收机响应于内部时钟信号从外部信号线采样数据。 寄存器存储一个表示定时偏移量的值，以调整数据采样的时间。 时钟电路产生内部时钟信号，使得内部时钟信号相对于外部时钟信号保持受控的定时关系。 时钟电路包括内插器，其相位混合一组参考时钟信号，使得内部时钟信号根据该值相位偏移。

公开(公告)号：US06496889B1

公开(公告)日：2002-12-17

申请号：US09398251

申请日：1999-08-16

申请人： Donald V. Perino ,  Haw-Jyh Liaw ,  Alfredo Moncayo ,  Kevin Donnelly ,  Richard M. Barth ,  Bruno W. Garlepp

发明人： Donald V. Perino ,  Haw-Jyh Liaw ,  Alfredo Moncayo ,  Kevin Donnelly ,  Richard M. Barth ,  Bruno W. Garlepp

IPC分类号： G06F1314

CPC分类号： H01L23/48 ,  G06F13/423 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

摘要翻译： 一种芯片到芯片的通信系统和接口技术。 主机和至少两个设备与高速总线的信号线相互连接。 采用电容耦合元件，例如二极管，将器件的接口电容耦合到信号线。 通过采用电容耦合元件以及支持电容信息传输的合适的信令技术，实现了信号线上的主设备和设备之间的高速信息传送速率。