公开(公告)号：US20060233291A1

公开(公告)日：2006-10-19

申请号：US11404502

申请日：2006-04-14

申请人： Bruno Garlepp ,  Jared Zerbe ,  Metha Jeeradit ,  Vladimir Stojanovic

发明人： Bruno Garlepp ,  Jared Zerbe ,  Metha Jeeradit ,  Vladimir Stojanovic

IPC分类号： H04L7/00

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second edge samples. The phase of the sampling clock signal is adjusted based, at least in part, on the first edge sample if the set of data samples matches a first data pattern and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

摘要翻译： 在集成电路器件内的接收电路中，响应于采样时钟信号的转变对二进制输入信号进行采样以产生一组数据采样。 另外将二进制输入信号与第一和第二阈值电平进行比较以产生相应的第一和第二边缘采样。 至少部分地基于第一边缘采样来调整采样时钟信号的相位，如果该组数据样本与第一数据模式匹配，并且至少部分地基于第二边缘采样，如果数据集合 样本匹配第二个数据模式。

公开(公告)号：US20050111585A1

公开(公告)日：2005-05-26

申请号：US10966070

申请日：2004-10-18

申请人： Vladimir Stojanovic ,  Mark Horowitz ,  Jared Zerbe ,  Anthony Bessios ,  Andrew Ho ,  Jason Wei ,  Grace Tsang ,  Bruno Garlepp

发明人： Vladimir Stojanovic ,  Mark Horowitz ,  Jared Zerbe ,  Anthony Bessios ,  Andrew Ho ,  Jason Wei ,  Grace Tsang ,  Bruno Garlepp

IPC分类号： H04L25/06 ,  H04L25/497 ,  G11B5/09

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

摘要翻译： 用于接收经由电信号导体发送的信号的接收电路。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

公开(公告)号：US20060170453A1

公开(公告)日：2006-08-03

申请号：US11368012

申请日：2006-03-03

申请人： Jared Zerbe ,  Bruno Garlepp ,  Pak Chau ,  Kevin Donnelly ,  Mark Horowitz ,  Stefanos Sidiropoulos ,  Billy Garrett ,  Carl Werner

发明人： Jared Zerbe ,  Bruno Garlepp ,  Pak Chau ,  Kevin Donnelly ,  Mark Horowitz ,  Stefanos Sidiropoulos ,  Billy Garrett ,  Carl Werner

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

摘要： A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

公开(公告)号：US20060120409A1

公开(公告)日：2006-06-08

申请号：US11327213

申请日：2006-01-05

申请人： Jared Zerbe ,  Kevin Donnelly ,  Stefanos Sidiropoulos ,  Donald Stark ,  Mark Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno Garlepp ,  Tsyr-Chyang Ho ,  Benedict Lau

发明人： Jared Zerbe ,  Kevin Donnelly ,  Stefanos Sidiropoulos ,  Donald Stark ,  Mark Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno Garlepp ,  Tsyr-Chyang Ho ,  Benedict Lau

IPC分类号： H04J3/06

CPC分类号： G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

公开(公告)号：US20050069067A1

公开(公告)日：2005-03-31

申请号：US10673677

申请日：2003-09-30

申请人： Jared Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Garlepp ,  Carl Werner

发明人： Jared Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Garlepp ,  Carl Werner

IPC分类号： H04L25/49 ,  H04L27/06

CPC分类号： H04L25/4917

摘要： A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.

摘要翻译： 公开了一种用于接收差分多PAM信号的技术。 在一个特定的示例性实施例中，该技术可以被实现为差分多PAM提取器电路。 在该特定示例性实施例中，差分多PAM提取器电路包括被配置为接收差分多PAM输入信号和第一差分参考信号的高LSB采样器电路，并且产生第一差分采样输出信号。 差分多PAM提取器电路还包括被配置为接收差分多PAM输入信号和第二差分参考信号的低LSB采样器电路，并且产生第二差分采样输出信号。 差分多PAM提取器电路还包括组合器电路，其被配置为接收第一差分采样输出信号和第二差分采样输出信号，并且产生指示差分多PAM输入信号的LSB值的差分LSB输出信号。

公开(公告)号：US20080049822A1

公开(公告)日：2008-02-28

申请号：US11871666

申请日：2007-10-12

申请人： Jared Zerbe ,  Vladimir Stojanovic ,  Fred Chen

发明人： Jared Zerbe ,  Vladimir Stojanovic ,  Fred Chen

IPC分类号： H04L27/01

CPC分类号： H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

摘要： A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

摘要翻译： 一种具有可选择抽头均衡器的信令电路。 信令电路包括缓冲器，选择电路和均衡电路。 缓冲器用于存储对应于在第一时间间隔期间在信令路径上发送的数据信号的多个数据值。 选择电路耦合到缓冲器，以根据选择值从多个数据值中选择数据值的子集。 均衡电路被耦合以从选择电路接收数据值的子集，并且适于根据数据值的子集来调整对应于在第二时间间隔期间在信令路径上发送的数据信号的信号电平。

公开(公告)号：US20060133538A1

公开(公告)日：2006-06-22

申请号：US11022469

申请日：2004-12-22

申请人： Vladimir Stojanovic ,  Amir Amirkhany ,  Jared Zerbe

发明人： Vladimir Stojanovic ,  Amir Amirkhany ,  Jared Zerbe

IPC分类号： H04L27/20 ,  H04L27/22

CPC分类号： H04L27/2637 ,  H04L5/06 ,  H04L27/2653

摘要： A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a baseband sub-channel and the passband circuit corresponds to a passband sub-channel. The first communication link circuit also includes a circuit that distributes a first subset of a data stream having a first symbol rate to the baseband circuit and a second subset of the data stream having a second symbol rate to the passband circuit. The baseband sub-channel and the passband sub-channel are separated by an adjacent guardband of frequencies. The passband carrier frequency is adjusted to define the guardband and the guardband corresponds to a first notch in a channel response of a first communications channel.

公开(公告)号：US20060133523A1

公开(公告)日：2006-06-22

申请号：US11022468

申请日：2004-12-22

申请人： Vladimir Stojanovic ,  Amir Amirkhany ,  Jared Zerbe

发明人： Vladimir Stojanovic ,  Amir Amirkhany ,  Jared Zerbe

IPC分类号： H04K1/10 ,  H04L27/20

CPC分类号： H04L25/03343 ,  H04L27/2637

摘要： A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal.

摘要翻译： 多音系统包括具有用于接收用于传输的数据流的接口的数据传输电路，分割数据流以产生多个子流的数据蒸汽分配器和多个并行数据准备电路。 每个数据准备电路准备相应的子流进行传输，并产生相应的子信道信号。 多个并行数据准备电路的至少第一数据准备电路包括用于对第一子流进行滤波的第一模拟滤波器。 第一模拟滤波器以大于第一子流的相应符号率的采样率操作。 第一模拟滤波器提供相应子信道信号的预加重和对应于相应子信道信号的相应频带之外的信号的衰减。 数据传输电路还包括用于组合各个子信道信号以产生数据传输信号的组合器。

公开(公告)号：US20070058744A1

公开(公告)日：2007-03-15

申请号：US11557101

申请日：2006-11-06

申请人： Amir Amirkhany ,  Vladimir Stojanovic ,  Elad Alon ,  Jared Zerbe ,  Mark Horowitz

发明人： Amir Amirkhany ,  Vladimir Stojanovic ,  Elad Alon ,  Jared Zerbe ,  Mark Horowitz

IPC分类号： H04K1/10 ,  H04J11/00 ,  G06F17/14

CPC分类号： G06F17/141 ,  G06J1/005

摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.

摘要翻译： 变换电路包括第一电路和第二电路。 第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。 第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。 每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。 第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。 每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

公开(公告)号：US08069378B2

公开(公告)日：2011-11-29

申请号：US12815382

申请日：2010-06-14

申请人： Jared Zerbe ,  Pak Shing Chau ,  William Franklin Stonecypher

发明人： Jared Zerbe ,  Pak Shing Chau ,  William Franklin Stonecypher

IPC分类号： G01R31/28

CPC分类号： H04L1/244 ,  G01R31/31703 ,  G01R31/31713 ,  G01R31/31716 ,  G01R31/31717 ,  G01R31/3183 ,  G01R31/31855 ,  G01R31/318577 ,  G01R31/3187 ,  G06F11/221 ,  G06F11/26 ,  G06F13/423 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/40 ,  H04B1/04 ,  H04B1/16 ,  H04B3/32 ,  H04B17/0085 ,  H04L1/0001 ,  H04L1/242 ,  H04L1/243 ,  H04L5/1438 ,  H04L25/03885

摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

摘要翻译： 描述了用于评估和优化信令系统的方法和装置。 在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。 在接收电路中产生类似的信息模式并用作参考。 接收电路比较图案。 模式之间的任何差异是可观察的。 在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。 本公开的实施例可以用各种类型的信令系统来实施，包括具有单端信号和具有差分信号的信令系统。 本公开的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统以及同时在单个导体上传送多个信息位的系统。