公开(公告)号：US09654117B1

公开(公告)日：2017-05-16

申请号：US15181857

申请日：2016-06-14

Applicant: COOPER TECHNOLOGIES COMPANY

Inventor： Ronald Landheer

IPC: H03L7/06 ,  H03L7/085

CPC classification number: H03L7/085 ,  H03L7/087 ,  H03L7/0991 ,  H03L2207/06

Abstract: An integrated circuit device implementing a digital phase-locked loop includes a measure period component, an averager component, a generator component, and a compensator component. In the digital phase-locked loop implementation, phase compensation and frequency compensation are separated from one another.

公开(公告)号：US10514997B2

公开(公告)日：2019-12-24

申请号：US15277683

申请日：2016-09-27

Applicant: COOPER TECHNOLOGIES COMPANY

Inventor： Ronald Landheer

IPC: G06F3/06 ,  G06F5/00 ,  G06F5/06 ,  G06F5/16 ,  G06F11/34

Abstract: Systems and methods associated with a multi-producer single consumer lock-free queue capable of accumulating traces is described herein. In a non-limiting embodiment, data is determined to be allocated, and a first head/tail pair indicating a location along a queue is received, the location indicating where a data bucket is able to be placed. A first data bucket to use for storing the data is determined, and the data is stored using the first data bucket. The first data bucket is then placed on the queue, and a first instruction to decrement a first reference count for the first head/tail pair is generated.

公开(公告)号：US10333736B2

公开(公告)日：2019-06-25

申请号：US15208093

申请日：2016-07-12

Applicant: COOPER TECHNOLOGIES COMPANY

Inventor： Ghislain Paquet ,  Alain Picotte ,  Remi Dutil ,  Ronald Landheer

IPC: H04L12/437 ,  H04L12/66 ,  H04L12/721 ,  H04L12/703 ,  H04L12/781

Abstract: A gateway for a computer network includes a programmable integrated circuit device, and a first port and a second port coupled to the programmable integrated circuit device. The programmable integrated circuit device is structured and configured to, responsive to a restoration of power to the gateway following a loss of power at the gateway, read configuration information stored by the gateway, and if indicated by the configuration information, forward first data traffic from the first port to the second port and forward second data traffic from second port to first port until the programmable integrated circuit device is configured to do otherwise.

公开(公告)号：US09973333B1

公开(公告)日：2018-05-15

申请号：US15340591

申请日：2016-11-01

Applicant: COOPER TECHNOLOGIES COMPANY

Inventor： Alain Picotte ,  Ronald Landheer ,  Hugues Bilodeau

IPC: H04L7/00 ,  H04L7/04 ,  G06F13/42

CPC classification number: H04L7/041 ,  G06F13/4282

Abstract: A bump-in-the-wire time code signal decoder and debugger apparatus includes a controller structured and configured to: receive an encoded time code signal, decode the encoded time code signal, and produce a parsed signal based on the decoding of the encoded time code signal. The apparatus also includes a communications interface coupled to the controller, wherein the communications interface is structured to receive the parsed signal and generate an output signal based on the parsed signal.