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公开(公告)号：US20240364353A1
公开(公告)日：2024-10-31
申请号：US18768179
申请日：2024-07-10
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US12063046B2
公开(公告)日：2024-08-13
申请号：US18063809
申请日：2022-12-09
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US12021538B2
公开(公告)日：2024-06-25
申请号：US17664364
申请日：2022-05-20
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Ajay M. Rao
CPC classification number: H03L7/083 , H03L7/085 , H03L7/0991
Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.
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公开(公告)号：US20240204786A1
公开(公告)日：2024-06-20
申请号：US18229161
申请日：2023-08-01
Applicant: Airoha Technology Corp.
Inventor： Chun-Yuan Huang , Chin-Chang Chang , Jeng-Hong Chen , Yun-Xuan Zhang
CPC classification number: H03L7/0991 , H03L7/0814
Abstract: A wireless communication device includes a receiver circuit, a phase shift control circuit, and a digital phase-locked loop (DPLL) circuit. The receiver circuit includes a down-converter circuit that is used to apply down-conversion to an input signal according to a local oscillator (LO) signal. The phase shift control circuit is used to generate a phase shift signal. The DPLL circuit is used to generate the LO signal locked to an initial frequency under a frequency-lock state. In response to the phase shift signal, the DPLL circuit is further used to make the LO signal have a different frequency without leaving the frequency-lock state.
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公开(公告)号：US20240187005A1
公开(公告)日：2024-06-06
申请号：US18076058
申请日：2022-12-06
Applicant: Silicon Laboratories Inc.
Inventor： John M. Khoury , Michael Wu
CPC classification number: H03L7/0991 , H03B5/32
Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11962314B2
公开(公告)日：2024-04-16
申请号：US17400851
申请日：2021-08-12
Applicant: SOCIONEXT INC.
Inventor： Kenichi Okada , Hanli Liu , Zheng Sun
CPC classification number: H03L7/0991 , G06F1/06 , G06F1/08 , H03K5/01 , H03M1/82 , H03K2005/00078
Abstract: With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.
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公开(公告)号：US11962313B2
公开(公告)日：2024-04-16
申请号：US16370479
申请日：2019-03-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen Victor Kosonocky , Mikhail Rodionov , Joyce Cheuk Wai Wong
CPC classification number: H03L7/0991 , H03K5/14 , H03K2005/00058
Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.
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公开(公告)号：US11923857B1
公开(公告)日：2024-03-05
申请号：US18102066
申请日：2023-01-26
Applicant: XILINX, INC.
Inventor： Hongtao Zhang , Ankur Jain , Yanfei Chen , Ronan Sean Casey , Winson Lin , Hsung Jai Im
CPC classification number: H03L7/0802 , H03L7/0991 , H03M1/82
Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.
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公开(公告)号：US20240056087A1
公开(公告)日：2024-02-15
申请号：US18448783
申请日：2023-08-11
Applicant: Microchip Technology Incorporated
Inventor： Youcef Fouzar , Waleed El-halwagy , William Roberts , Kristopher Kshonze , Faizal Warsalee
CPC classification number: H03L7/0991 , H03L7/104
Abstract: A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.
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公开(公告)号：US20240022390A1
公开(公告)日：2024-01-18
申请号：US17812926
申请日：2022-07-15
Applicant: Hughes Network Systems
Inventor： Neal David Becker
CPC classification number: H04L7/0025 , H03L7/0991
Abstract: An apparatus for synchronizing frequency to a symbol timing, the apparatus including: a master oscillator to generate a master clock signal; an interpolator to accumulate a frequency error estimate between a symbol timing frequency and the master clock signal; and a frequency controller to transfer a portion of the frequency error estimate to the master oscillator to obtain a lock between the symbol timing and the master clock signal of the master oscillator in a manner that zeros-out the frequency error estimate.
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