公开(公告)号：US20140329385A1

公开(公告)日：2014-11-06

申请号：US14351828

申请日：2012-10-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD

Inventor： Hsiao-Chia Wu ,  Shilin Fang ,  Tse-Huang Lo ,  Zhengpei Chen ,  Shu Zhang

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76837 ,  H01L21/76838 ,  H01L24/03

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

Abstract translation: 一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。 在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。 在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度 的4μm金属凹凸结构。 使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。 最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。

公开(公告)号：US09236306B2

公开(公告)日：2016-01-12

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

Abstract translation: 根据本说明书的制造半导体器件的方法解决了现有技术中的问题，即LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件的击穿。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 该方法适用于BCD处理等。

公开(公告)号：US20140147980A1

公开(公告)日：2014-05-29

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: The present invention relates to the technical field of semiconductor manufacturing. A method for manufacturing a semiconductor device is disclosed, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the like.

Abstract translation: 本发明涉及半导体制造技术领域。 公开了一种用于制造半导体器件的方法，其解决了现有技术中在LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件破坏的问题。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 本发明的实施例可应用于BCD处理等。

公开(公告)号：US08956972B2

公开(公告)日：2015-02-17

申请号：US14351828

申请日：2012-10-12

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Hsiao-Chia Wu ,  Shilin Fang ,  Tse-Huang Lo ,  Zhengpei Chen ,  Shu Zhang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76837 ,  H01L21/76838 ,  H01L24/03

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

Abstract translation: 一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。 在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。 在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度 的4μm金属凹凸结构。 使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。 最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。