公开(公告)号：US20160099347A1

公开(公告)日：2016-04-07

申请号：US14891470

申请日：2014-05-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shu Zhang ,  Guangtao Han ,  Guipeng Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/426 ,  H01L21/027

CPC classification number: H01L29/7816 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/426 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

Abstract translation: 本发明提供一种横向扩散的金属氧化物半导体器件的制造方法，包括以下步骤：在晶片的基板上生长氧化物层（S210）; 在晶片的表面上涂覆光致抗蚀剂（S220）; 通过使用第一光刻掩模进行光蚀刻，以及在显影后曝光第一植入窗口（S230）; 经由所述第一注入窗进行离子注入以在所述衬底中形成漂移区（S240）; 在去除光致抗蚀剂之后再次在晶片表面上涂覆一层光致抗蚀剂（S250）; 通过使用漂移区域的氧化物层的光刻掩模来执行光刻（S260）; 并蚀刻氧化层以形成漂移区的氧化物层（S270）。 还提供了横向扩散的金属氧化物半导体器件。

公开(公告)号：US20140329385A1

公开(公告)日：2014-11-06

申请号：US14351828

申请日：2012-10-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD

Inventor： Hsiao-Chia Wu ,  Shilin Fang ,  Tse-Huang Lo ,  Zhengpei Chen ,  Shu Zhang

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76837 ,  H01L21/76838 ,  H01L24/03

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

Abstract translation: 一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。 在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。 在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度 的4μm金属凹凸结构。 使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。 最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。

公开(公告)号：US09768292B2

公开(公告)日：2017-09-19

申请号：US14891470

申请日：2014-05-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shu Zhang ,  Guangtao Han ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/426

CPC classification number: H01L29/7816 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/426 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

公开(公告)号：US09356137B2

公开(公告)日：2016-05-31

申请号：US14130483

申请日：2013-05-07

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Shu Zhang ,  Yanqiang He ,  TseHuang Lo ,  HsiaoChia Wu

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/482

CPC classification number: H01L29/7816 ,  H01L23/4824 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L29/7835 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Abstract translation: 公开了功率MOS器件结构的各种实施例。 一方面，功率MOS器件结构包括多个LDMOS和多个接合焊盘。 LDMOS的基本单元并联并电耦合到焊盘，以耦合到LDMOS的每个基本单元的栅极端子，源极端子，漏极端子和衬底。 LDMOS的基本单元设置在焊盘下方。 接合焊盘包括厚度为3.5μm至4.5μm，宽度为1.5μm至2.5μm的单层金属。 本公开的功率MOS器件的焊盘下方的区域用于增加LDMOS的基本单元的数量，从而有效地降低导通电阻。

公开(公告)号：US09236306B2

公开(公告)日：2016-01-12

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

Abstract translation: 根据本说明书的制造半导体器件的方法解决了现有技术中的问题，即LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件的击穿。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 该方法适用于BCD处理等。

公开(公告)号：US09252240B2

公开(公告)日：2016-02-02

申请号：US14436016

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jian Xu ,  Min He ,  Shu Zhang ,  Zehuang Luo ,  Xiaojia Wu

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/311 ,  H01L29/40

CPC classification number: H01L29/66681 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76213 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/408

Abstract: A manufacturing method for a semiconductor device with a discrete field oxide structure is provided, the method includes: growing a first PAD oxide layer on the surface of a wafer; forming a first silicon nitride layer (302) on the first PAD oxide layer through deposition; defining a field region by photolithography and etching same to remove the first silicon nitride layer (302) located on the field region; performing an ion implantation process to the field region; performing field region oxidation to grow a field oxide layer (304); peeling off the first silicon nitride layer (302); wet-dipping the wafer to remove the first PAD oxide layer and a part of field oxide layer (304); growing a second PAD oxide layer on the surface of the wafer, and forming a second silicon nitride layer (312) on the second PAD oxide layer through deposition; defining a drift region by photolithography and etching same to remove the second silicon nitride layer (312) on the drift region; performing an ion implantation process to the drift region; and performing drift region oxidation to grow a drift region oxide layer (314). The above-mentioned method peels off the silicon nitride layer (302) after the growth of the field oxide layer (304) is finished, at this time, the length of a bird beak of field-oxide (304) can be optimized by adjusting a wet-dipping amount to solve the problem that the bird beak of field-oxide (304) is too long.

Abstract translation: 提供一种具有离散场氧化物结构的半导体器件的制造方法，该方法包括：在晶片表面上生长第一PAD氧化物层; 通过沉积在所述第一PAD氧化物层上形成第一氮化硅层（302）; 通过光刻法定义场区域并进行蚀刻以去除位于场区域上的第一氮化硅层（302）; 对场区进行离子注入工艺; 进行场区氧化以生长场氧化物层（304）; 剥离第一氮化硅层（302）; 湿浸湿晶片以去除第一PAD氧化物层和一部分场氧化物层（304）; 在所述晶片的表面上生长第二PAD氧化物层，并且通过沉积在所述第二PAD氧化物层上形成第二氮化硅层（312）; 通过光刻法定义漂移区域并进行蚀刻以去除漂移区域上的第二氮化硅层（312）; 对漂移区域进行离子注入工艺; 以及进行漂移区氧化以生长漂移区氧化物层（314）。 上述方法在场氧化物层（304）的生长完成之后，剥离氮化硅层（302），此时可以通过调整场氧化物（304）的鸟喙的长度来优化 用于解决场氧化物（304）的鸟喙太长的问题的湿浸量。

公开(公告)号：US20140147980A1

公开(公告)日：2014-05-29

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: The present invention relates to the technical field of semiconductor manufacturing. A method for manufacturing a semiconductor device is disclosed, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the like.

Abstract translation: 本发明涉及半导体制造技术领域。 公开了一种用于制造半导体器件的方法，其解决了现有技术中在LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件破坏的问题。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 本发明的实施例可应用于BCD处理等。

公开(公告)号：US20150295069A1

公开(公告)日：2015-10-15

申请号：US14436016

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jian Xu ,  Min He ,  Shu Zhang ,  Zehuang Luo ,  Xiaojia Wu

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/66681 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76213 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/408

Abstract: A manufacturing method for a semiconductor device with a discrete field oxide structure is provided, the method includes: growing a first PAD oxide layer on the surface of a wafer; forming a first silicon nitride layer (302) on the first PAD oxide layer through deposition; defining a field region by photolithography and etching same to remove the first silicon nitride layer (302) located on the field region; performing an ion implantation process to the field region; performing field region oxidation to grow a field oxide layer (304); peeling off the first silicon nitride layer (302); wet-dipping the wafer to remove the first PAD oxide layer and a part of field oxide layer (304); growing a second PAD oxide layer on the surface of the wafer, and forming a second silicon nitride layer (312) on the second PAD oxide layer through deposition; defining a drift region by photolithography and etching same to remove the second silicon nitride layer (312) on the drift region; performing an ion implantation process to the drift region; and performing drift region oxidation to grow a drift region oxide layer (314). The above-mentioned method peels off the silicon nitride layer (302) after the growth of the field oxide layer (304) is finished, at this time, the length of a bird beak of field-oxide (304) can be optimized by adjusting a wet-dipping amount to solve the problem that the bird beak of field-oxide (304) is too long.

Abstract translation: 提供一种具有离散场氧化物结构的半导体器件的制造方法，该方法包括：在晶片表面上生长第一PAD氧化物层; 通过沉积在所述第一PAD氧化物层上形成第一氮化硅层（302）; 通过光刻法定义场区域并进行蚀刻以去除位于场区域上的第一氮化硅层（302）; 对场区进行离子注入工艺; 进行场区氧化以生长场氧化物层（304）; 剥离第一氮化硅层（302）; 湿浸湿晶片以去除第一PAD氧化物层和一部分场氧化物层（304）; 在所述晶片的表面上生长第二PAD氧化物层，并且通过沉积在所述第二PAD氧化物层上形成第二氮化硅层（312）; 通过光刻法定义漂移区域并进行蚀刻以去除漂移区域上的第二氮化硅层（312）; 对漂移区域进行离子注入工艺; 以及进行漂移区氧化以生长漂移区氧化物层（314）。 上述方法在场氧化物层（304）的生长完成之后，剥离氮化硅层（302），此时可以通过调整场氧化物（304）的鸟喙的长度来优化 用于解决场氧化物（304）的鸟喙太长的问题的湿浸量。

公开(公告)号：US08956972B2

公开(公告)日：2015-02-17

申请号：US14351828

申请日：2012-10-12

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Hsiao-Chia Wu ,  Shilin Fang ,  Tse-Huang Lo ,  Zhengpei Chen ,  Shu Zhang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76837 ,  H01L21/76838 ,  H01L24/03

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

Abstract translation: 一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。 在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。 在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度 的4μm金属凹凸结构。 使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。 最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。