公开(公告)号：US11088132B2

公开(公告)日：2021-08-10

申请号：US16329665

申请日：2017-08-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang Wang

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/60 ,  H02H9/00

Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.

公开(公告)号：US10381343B2

公开(公告)日：2019-08-13

申请号：US15569848

申请日：2016-04-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun Sun ,  Zhongyu Lin ,  Guangyang Wang ,  Guipeng Sun

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/87 ,  H01L29/40

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well (330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

公开(公告)号：US11264468B2

公开(公告)日：2022-03-01

申请号：US16772031

申请日：2019-01-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang Wang

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a field oxide layer, a gate region and field plate integrated structure and a plurality of contact holes. A body region and a drift region are formed in the semiconductor substrate. An active region is formed in the body region, and a drain region is formed in the drift region. A field oxide layer is located on the drift region and the drift region surrounds a part of the field oxide layer. An integrated structure including a gate region and a field plate, the integrated structure extending from above the field oxide layer to above the body region. A depth of a contact hole closer to the source region penetrating into the field oxide layer is greater than a depth of a contact hole closer to the drain region penetrating into the field oxide layer.