公开(公告)号：US10811520B2

公开(公告)日：2020-10-20

申请号：US16462432

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall; removing the second dielectric layer (240) in the source region side wall and retaining the first dielectric layer (230) therein.

公开(公告)号：US11552164B2

公开(公告)日：2023-01-10

申请号：US17265565

申请日：2019-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L21/22 ,  H01L21/26 ,  H01L29/06 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

公开(公告)号：US11158737B2

公开(公告)日：2021-10-26

申请号：US16644856

申请日：2018-08-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun ,  Hongfeng Jin

IPC: H01L29/78 ,  H01L29/66

Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.

公开(公告)号：US11127840B2

公开(公告)日：2021-09-21

申请号：US16481576

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L21/763 ,  H01L21/473 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762

Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.

公开(公告)号：US10290705B2

公开(公告)日：2019-05-14

申请号：US15564181

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Feng Huang ,  Guangtao Han ,  Guipeng Sun ,  Feng Lin ,  Longjie Zhao ,  Huatang Lin ,  Bing Zhao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/76 ,  H01L29/06 ,  H01L21/762

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

公开(公告)号：US10199495B2

公开(公告)日：2019-02-05

申请号：US15766082

申请日：2016-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

公开(公告)号：US11462628B2

公开(公告)日：2022-10-04

申请号：US16771168

申请日：2018-11-13

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L31/062 ,  H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

公开(公告)号：US10381343B2

公开(公告)日：2019-08-13

申请号：US15569848

申请日：2016-04-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun Sun ,  Zhongyu Lin ,  Guangyang Wang ,  Guipeng Sun

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/87 ,  H01L29/40

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well (330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

公开(公告)号：US10014392B2

公开(公告)日：2018-07-03

申请号：US15564172

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guangsheng Zhang ,  Guipeng Sun ,  Sen Zhang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

公开(公告)号：US12224340B2

公开(公告)日：2025-02-11

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang Liu ,  Chi Zhang ,  Kui Xiao ,  Guipeng Sun ,  Dejin Wang ,  Jiaxing Wei ,  Li Lu ,  Weifeng Sun ,  Shengli Lu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.