公开(公告)号：US07626793B2

公开(公告)日：2009-12-01

申请号：US11339786

申请日：2006-01-25

申请人： Cetin Kaya ,  James Teng ,  Claus Neesgaard

发明人： Cetin Kaya ,  James Teng ,  Claus Neesgaard

IPC分类号： H02H3/08 ,  H02H9/02 ,  H02H3/00

CPC分类号： H03K17/082

摘要： A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or negative currents through the FET can be measured to determine whether an overcurrent condition exists. By measuring positive and negative currents in the FET, the overcurrent detector can obtain twice as much information as when measuring a positive current alone, and can respond more readily to overcurrent conditions. The overcurrent detector avoids the constraints typically observed in cycle-by-cycle PWM control with single polarity Vds sensing, while permitting a relaxation in the timing requirements for current sensing. A spike suppression circuit also contributes to longer sensing intervals.

摘要翻译： 用于确定FET中的过电流的电路和方法以正负极性检测FET的输出电压。 可以测量通过FET的相关正或负电流以确定是否存在过电流状况。 通过测量FET中的正电流和负电流，过电流检测器可以获得与单独测量正电流时相同的信息量的两倍，并且可以更容易地响应过电流条件。 过电流检测器避免了在单极性Vds感测的逐周期PWM控制中通常观察到的约束，同时允许电流感测的定时要求松弛。 尖峰抑制电路还有助于更长的感测间隔。

公开(公告)号：US20070171591A1

公开(公告)日：2007-07-26

申请号：US11339786

申请日：2006-01-25

申请人： Cetin Kaya ,  James Teng ,  Claus Neesgaard

发明人： Cetin Kaya ,  James Teng ,  Claus Neesgaard

IPC分类号： H02H3/00

CPC分类号： H03K17/082

摘要： A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or negative currents through the FET can be measured to determine whether an overcurrent condition exists. By measuring positive and negative currents in the FET, the overcurrent detector can obtain twice as much information as when measuring a positive current alone, and can respond more readily to overcurrent conditions. The overcurrent detector avoids the constraints typically observed in cycle-by-cycle PWM control with single polarity Vds sensing, while permitting a relaxation in the timing requirements for current sensing. A spike suppression circuit also contributes to longer sensing intervals.

摘要翻译： 用于确定FET中的过电流的电路和方法以正负极性检测FET的输出电压。 可以测量通过FET的相关正或负电流以确定是否存在过电流状况。 通过测量FET中的正电流和负电流，过电流检测器可以获得与单独测量正电流时相同的信息量的两倍，并且可以更容易地响应过电流条件。 过电流检测器避免了在单极性Vds感测的逐周期PWM控制中通常观察到的约束，同时允许电流感测的定时要求松弛。 尖峰抑制电路还有助于更长的感测间隔。

公开(公告)号：US07317355B2

公开(公告)日：2008-01-08

申请号：US11125968

申请日：2005-05-10

申请人： Shifeng Zhao ,  Cetin Kaya ,  James Teng ,  Claus Neesgaard ,  Lieyi Fang ,  Jeff Berwick

发明人： Shifeng Zhao ,  Cetin Kaya ,  James Teng ,  Claus Neesgaard ,  Lieyi Fang ,  Jeff Berwick

IPC分类号： H03F3/217

CPC分类号： H03K17/0822 ,  H03K17/162

摘要： A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

摘要翻译： 提供了用于检测功率场效应晶体管（FET）中的过电流状态的系统和方法。 在一个实施例中，用于检测功率FET中的过电流状态的过电流检测电路包括用于产生参考电流的电流发生器电路和用于接收参考电流并提供参考电压的多个匹配FET， 匹配的FET彼此匹配并连接到功率FET。 过电流检测电路还包括比较器，用于测量功率FET的漏极 - 源极电压，并提供指示功率FET的漏极 - 源极电压已经超过参考电压的输出。

公开(公告)号：US20060256492A1

公开(公告)日：2006-11-16

申请号：US11125968

申请日：2005-05-10

申请人： Shifeng Zhao ,  Cetin Kaya ,  James Teng ,  Claus Neesgaard ,  Lieyi Fang ,  Jeff Berwick

发明人： Shifeng Zhao ,  Cetin Kaya ,  James Teng ,  Claus Neesgaard ,  Lieyi Fang ,  Jeff Berwick

IPC分类号： H02H3/08

CPC分类号： H03K17/0822 ,  H03K17/162

摘要： A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

摘要翻译： 提供了用于检测功率场效应晶体管（FET）中的过电流状态的系统和方法。 在一个实施例中，用于检测功率FET中的过电流状态的过电流检测电路包括用于产生参考电流的电流发生器电路和用于接收参考电流并提供参考电压的多个匹配FET， 匹配的FET彼此匹配并连接到功率FET。 过电流检测电路还包括比较器，用于测量功率FET的漏极 - 源极电压，并提供指示功率FET的漏极 - 源极电压已经超过参考电压的输出。

公开(公告)号：US07705673B2

公开(公告)日：2010-04-27

申请号：US11970289

申请日：2008-01-07

申请人： James Teng ,  Qiong M. Li ,  Cetin Kaya

发明人： James Teng ,  Qiong M. Li ,  Cetin Kaya

IPC分类号： H03F21/00

CPC分类号： H03F3/2173 ,  H03F1/523 ,  H03F2200/03 ,  H03F2200/351

摘要： Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM−. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FET1 driven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FET2 during the much longer conduction time of FET2 driven by PWM−. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FET2 during its conduction time. The resulting drain to source voltage of FET2 is measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current. A second Negative Current Sense circuit is utilized to similarly detect over-current conditions when the pulse width of PWM− becomes too narrow for reliable operation of prior art over-current protection circuits, thus protecting both FETs in the class D output stage from excessive current.

摘要翻译： D类输出级的两个晶体管由互补的可变占空比信号PWM +和PWM-驱动。 当PWM +信号的脉冲宽度变得太窄，以便于感测由PWM +驱动的FET1的漏极 - 源极电压的现有技术的过电流保护电路的可靠操作时，窄脉冲检测器产生指示该窄脉冲条件的信号。 在由PWM驱动的FET2的更长的导通时间内，负电流检测电路测量FET2两端的漏源电压。 由于存储在串联电感器中的能量耦合到D级的输出端，所以在其导通时间期间，负电流流过该FET2。 测量FET2的所得到的源极到源极电压并将其与阈值进行比较。 如果指示电流的电压超过阈值，并且窄脉冲检测器输出指示窄脉冲条件，则产生减少电流的禁止信号。 使用第二负电流检测电路来类似地检测当PWM的脉冲宽度变得太窄以致于现有技术的过电流保护电路的可靠操作时的过电流状况，从而保护D类输出级中的两个FET免受过大的电流 。

公开(公告)号：US20090174485A1

公开(公告)日：2009-07-09

申请号：US11970289

申请日：2008-01-07

申请人： James Teng ,  Qiong M. Li ,  Cetin Kaya

发明人： James Teng ,  Qiong M. Li ,  Cetin Kaya

IPC分类号： H03F1/52 ,  H03F3/217

CPC分类号： H03F3/2173 ,  H03F1/523 ,  H03F2200/03 ,  H03F2200/351

摘要： Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM−. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FET1 driven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FET2 during the much longer conduction time of FET2 driven by PWM−. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FET2 during its conduction time. The resulting drain to source voltage of FET2 is measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current. A second Negative Current Sense circuit is utilized to similarly detect over-current conditions when the pulse width of PWM− becomes too narrow for reliable operation of prior art over-current protection circuits, thus protecting both FETs in the class D output stage from excessive current.

摘要翻译： D类输出级的两个晶体管由互补的可变占空比信号PWM +和PWM-驱动。 当PWM +信号的脉冲宽度变得太窄，以便于感测由PWM +驱动的FET1的漏极 - 源极电压的现有技术的过电流保护电路的可靠操作时，窄脉冲检测器产生指示该窄脉冲条件的信号。 在由PWM驱动的FET2的更长的导通时间内，负电流检测电路测量FET2两端的漏源电压。 由于存储在串联电感器中的能量耦合到D级的输出端，所以在其导通时间期间，负电流流过该FET2。 测量FET2的所得到的源极到源极电压并将其与阈值进行比较。 如果指示电流的电压超过阈值，并且窄脉冲检测器输出指示窄脉冲条件，则产生减少电流的禁止信号。 使用第二负电流检测电路来类似地检测当PWM的脉冲宽度变得太窄以致于现有技术的过电流保护电路的可靠操作时的过电流状况，从而保护D类输出级中的两个FET免受过大的电流 。

公开(公告)号：US06797935B2

公开(公告)日：2004-09-28

申请号：US10251732

申请日：2002-09-20

申请人： Cetin Kaya ,  Julian Chen

发明人： Cetin Kaya ,  Julian Chen

IPC分类号： H01L3100

CPC分类号： H04N5/3745 ,  H01L27/14609

摘要： A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and optical response of active pixel arrays, and improves the scalability of the pixel element.

摘要翻译： 正向偏置二极管40用于对光电二极管26充电，而不是NMOS晶体管。 该光电二极管充电机构增加了有源像素阵列的动态范围和光学响应，并提高了像素元件的可扩展性。

公开(公告)号：US06306690B1

公开(公告)日：2001-10-23

申请号：US09389144

申请日：1999-09-02

申请人： Cetin Kaya ,  Stanton P. Ashburn

发明人： Cetin Kaya ,  Stanton P. Ashburn

IPC分类号： H01L21332

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region. The second region and the third region are masked, leaving the first region unmasked. Then, at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer is removed from the first region. A second dielectric layer is formed outwardly from the substrate and the first dielectric layer in a region approximately coextensive with the first region and the third regions, respectively.

摘要翻译： 本发明包括集成电路，包括集成的高电压和低电压外围晶体管以及用于制造集成电路的方法。 在本发明的一个方面，一种将高压和低压晶体管集成到浮动栅极存储器阵列中的方法包括以下步骤：从半导体衬底向外形成隧道氧化层，形成从隧道氧化物层向外设置的浮动栅层;以及 形成从所述浮栅层向外设置以形成第一中间结构的绝缘体层。 该方法还包括以下步骤：掩蔽第一中间结构的第一区域和第二区域，留下未被掩蔽的第三区域，从第三区域去除绝缘体层，浮动栅极层和隧道氧化物层的至少一部分，以及 形成在与所述第三区域大致共同延伸的区域中从所述基板向外设置的第一介电层。 第二个区域和第三个区域被掩盖，使第一个区域被隐藏。 然后，从第一区域去除绝缘体层，浮栅和隧道氧化物层的至少一部分。 在与第一区域和第三区域大致共同延伸的区域中，从基板和第一介电层向外形成第二电介质层。

公开(公告)号：US6072212A

公开(公告)日：2000-06-06

申请号：US978361

申请日：1997-11-25

申请人： Cetin Kaya ,  Kemal Tamer San

发明人： Cetin Kaya ,  Kemal Tamer San

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation. Therefore, there is no need for wordline (15) decoding of large arrays. In addition to the above features, use of the cell array of this invention saves space by eliminating, in certain types of prior-art arrays, the need for space-consuming columnar metal source lines. In that same type of array, a self-aligned-source etch step and a self-aligned-source implant step are eliminated.

摘要翻译： 本发明提供了一种成本有效的易于集成的闪存EPROM单元阵列。 从第一导电类型的衬底（31）开始，第二导电类型的第一扩散（30）形成源极（11）以及阵列的所有存储器单元（10）的源极之间的连接。 第一导电型的第二扩散（32）形成阵列中的至少一个存储单元（10）的沟道。 该存储单元（10）的浮动栅极（13）和控制栅极（14）位于第一扩散部分和第二扩散部分之间并与其绝缘。 在第二扩散（32）中隔离第二导电类型的第三扩散（33）以形成存储单元（10）的漏极（12）。 在操作期间，只有正电压可用于对电池（10）进行编程和擦除，从而消除对负电压和三阱扩散的需要。 本发明的电池阵列对于Fowler-Nordheim擦除操作需要很少的或没有电流。 因此，不需要对大阵列进行字线（15）解码。 除了上述特征之外，本发明的电池阵列的使用通过在某些类型的现有技术的阵列中消除对空间消耗的柱状金属源极线的需求来节省空间。 在相同类型的阵列中，消除了自对准源蚀刻步骤和自对准源注入步骤。

公开(公告)号：US5482880A

公开(公告)日：1996-01-09

申请号：US66816

申请日：1993-05-24

申请人： Cetin Kaya ,  David Liu

发明人： Cetin Kaya ,  David Liu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/7886

摘要： In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.

摘要翻译： 在一个实施例中，非易失性存储单元结构10包括形成在半导体衬底8的表面中并被沟道区21分隔的重掺杂源极11和漏极12区域。浮置栅极13形成在沟道上并与沟道绝缘 区域21和控制栅极14形成在浮置栅极13之上并与浮动栅极13绝缘。轻掺杂区域20形成在浮置栅极13下方的沟道21中并与源极区域11相邻。轻掺杂区域20与 还公开了其它实施方案和方法。