公开(公告)号：US07485917B2

公开(公告)日：2009-02-03

申请号：US11390144

申请日：2006-03-28

Applicant: Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

Inventor： Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

IPC: H01L29/788

CPC classification number: H01L29/7886 ,  H01L21/28273 ,  H01L29/42328

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract translation: 公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。 电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。 盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。 电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。 此外，设置形成在第三绝缘层上的擦除栅极。

公开(公告)号：US20070093024A1

公开(公告)日：2007-04-26

申请号：US11390144

申请日：2006-03-28

Applicant: Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

Inventor： Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7886 ,  H01L21/28273 ,  H01L29/42328

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract translation: 公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。 电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。 盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。 电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。 此外，设置形成在第三绝缘层上的擦除栅极。

公开(公告)号：US20070015331A1

公开(公告)日：2007-01-18

申请号：US11458847

申请日：2006-07-20

Applicant: Leonard Forbes

Inventor： Leonard Forbes

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C2216/28 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/7886

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Abstract translation: 提供NOR闪存单元，阵列和系统的结构和方法。 NOR闪存单元包括从衬底向外延伸的垂直浮栅晶体管。 具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的沟道区域的浮置栅极晶体管，通过栅极绝缘体与沟道区域分离的浮动栅极和控制栅极 通过栅极电介质与浮动栅极分离。 源极线形成在与垂直浮栅晶体管相邻的沟槽中并耦合到第一源/漏区。 耦合到第二源/漏区的传输线。 并且，字线连接到垂直于源极线的控制门。

公开(公告)号：US07130216B2

公开(公告)日：2006-10-31

申请号：US10788230

申请日：2004-02-26

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: G11C16/04

CPC classification number: H01L21/28273 ,  G11C16/0416 ,  H01L27/108 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7886 ,  H01L29/8611 ,  H01L29/872

Abstract: One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and the second diffusion region. The memory cell includes a gate insulator stack formed above the channel region, and a gate to connect to a word line. The gate insulator stack includes a floating plate to selectively hold a charge. The floating plate is connected to the second diffusion region. The memory cell includes a diode that connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. Other aspects are provided herein.

公开(公告)号：US07113429B2

公开(公告)日：2006-09-26

申请号：US11006312

申请日：2004-12-06

Applicant: Leonard Forbes

Inventor： Leonard Forbes

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C2216/28 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/7886

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

公开(公告)号：US20050085040A1

公开(公告)日：2005-04-21

申请号：US11005909

申请日：2004-12-06

Applicant: Leonard Forbes

Inventor： Leonard Forbes

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C2216/28 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/7886

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Abstract translation: 提供NOR闪存单元，阵列和系统的结构和方法。 NOR闪存单元包括从衬底向外延伸的垂直浮栅晶体管。 具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的沟道区域的浮置栅极晶体管，通过栅极绝缘体与沟道区域分离的浮动栅极和控制栅极 通过栅极电介质与浮动栅极分离。 源极线形成在与垂直浮栅晶体管相邻的沟槽中并耦合到第一源/漏区。 耦合到第二源/漏区的传输线。 并且，字线连接到垂直于源极线的控制门。

公开(公告)号：US20040160825A1

公开(公告)日：2004-08-19

申请号：US10788230

申请日：2004-02-26

Applicant: Micron Technology, Inc.

Inventor： Arup Bhattacharyya

IPC: G11C011/34

CPC classification number: H01L21/28273 ,  G11C16/0416 ,  H01L27/108 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7886 ,  H01L29/8611 ,  H01L29/872

Abstract: One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and the second diffusion region. The memory cell includes a gate insulator stack formed above the channel region, and a gate to connect to a word line. The gate insulator stack includes a floating plate to selectively hold a charge. The floating plate is connected to the second diffusion region. The memory cell includes a diode that connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. Other aspects are provided herein.

Abstract translation: 本主题的一个方面涉及一个单一设备非易失性存储单元。 存储单元包括在体区中形成的体区，第一扩散区和第二扩散区。 在第一扩散区域和第二扩散区域之间的体区域中形成沟道区域。 存储单元包括形成在通道区域上方的栅极绝缘体堆叠以及连接到字线的栅极。 栅极绝缘体堆叠包括用于选择性地保持电荷的浮动板。 浮板连接到第二扩散区。 存储单元包括将体区域连接到第二扩散区域的二极管，使得当二极管被反向偏置时浮置板被充电。 本文提供了其他方面。

公开(公告)号：US20030235079A1

公开(公告)日：2003-12-25

申请号：US10177483

申请日：2002-06-21

Applicant: Micron Technology, Inc.

Inventor： Leonard Forbes

IPC: G11C011/34

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C2216/28 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/7886

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Abstract translation: 提供NOR闪存单元，阵列和系统的结构和方法。 NOR闪存单元包括从衬底向外延伸的垂直浮栅晶体管。 具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的沟道区域的浮置栅极晶体管，通过栅极绝缘体与沟道区域分离的浮动栅极和控制栅极 通过栅极电介质与浮动栅极分离。 源极线形成在与垂直浮栅晶体管相邻的沟槽中并耦合到第一源/漏区。 耦合到第二源/漏区的传输线。 并且，字线连接到垂直于源极线的控制门。

公开(公告)号：US20030218203A1

公开(公告)日：2003-11-27

申请号：US10152107

申请日：2002-05-21

Applicant: Taiwan Semiconductor Manufacturing Company

Inventor： Chia-Ta Hsieh

IPC: H01L029/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7886

Abstract: A new split gate structure is disclosed with improved programming efficiency. A silicon region, extending to the surface of a semiconductor substrate, has parallel source/drain regions and electrical connecting regions disposed over the source/drain region. A multiplicity of structures is situated between source drain regions. Each structure is composed of two tower structures and intervening oxide layers. A floating gate tower, in which a gate oxide layer separates a floating gate from said silicon region and an insulating layer separates said floating gate from a top gate, with a nitride layer disposed over the top gate. And a selected gate tower in which a silicon pedestal is in intimate electrical contact with said silicon region and said silicon pedestal is separated from a selected gate by an insulating layer. Along the interfacing sidewalls, the silicon pedestal is separated from the floating gate by a first intervening oxide layer and the selected gate is separated from the floating gate tower by a second intervening oxide layer.

Abstract translation: 公开了一种新的分割门结构，其具有改进的编程效率。 延伸到半导体衬底的表面的硅区域具有平行的源极/漏极区域和设置在源极/漏极区域上的电连接区域。 多个结构位于源极漏极区之间。 每个结构由两个塔结构和中间氧化物层组成。 一种浮栅塔，其中栅极氧化层将浮栅与所述硅区分开，并且绝缘层将所述浮栅与顶栅隔开，氮化物层设置在顶栅上。 并且其中硅基座与所述硅区域紧密电接触并且所述硅基座的选定门塔通过绝缘层与选定的栅极分离。 沿着接口侧壁，硅基座通过第一中间氧化物层与浮动栅极分离，并且所选择的栅极通过第二介入氧化物层与浮动栅极塔分离。

公开(公告)号：US20010038119A1

公开(公告)日：2001-11-08

申请号：US09873451

申请日：2001-06-05

Inventor： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC: H01L029/788

CPC classification number: H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

Abstract: A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.

Abstract translation: 一种制造具有非易失性存储单元的半导体存储器件的方法，每个半导体存储器单元均由具有浮置栅极和控制栅极以及第一和第二半导体区域的MISFET构成。 通过该方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是，在第二半导体区域的形成中引入较低剂量的砷。 第一半导体区域形成为具有大于第二半导体区域的结深度的结深度，并且第一和第二半导体区域都具有在浮栅电极下延伸的部分。 存储在浮置栅电极中的载体通过隧穿穿过浮栅电极下方的绝缘膜而在浮置栅极电极和第一半导体区域之间传输。 该方法还特征在于外围电路的MISFET的形成。