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6 条记录 (耗时 0.025 秒)

    Baseband signal processor
    1.
    发明申请
    Baseband signal processor 审中-公开
    基带信号处理器

    公开(公告)号：US20060255996A1

    公开(公告)日：2006-11-16

    申请号：US11398060

    申请日：2006-04-04

    申请人： Chin Li ,  Paul Sheehy ,  Eoin Carey ,  Gerard Quilligan ,  Walid Ahmed

    发明人： Chin Li ,  Paul Sheehy ,  Eoin Carey ,  Gerard Quilligan ,  Walid Ahmed

    IPC分类号： H03M1/12

    CPC分类号： H04W52/52 ,  H03F1/26 ,  H03F3/211 ,  H03F3/24 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/331 ,  H03F2203/45356 ,  H03H11/1291 ,  H03H11/245 ,  H03M1/0854 ,  H03M1/66

    摘要： A power control module receives a dynamic power control signal and generates a differential bias signal proportional to the dynamic power control signal. An analog multiplexer receives a digital amplitude signal including n bits and receives the differential bias signal. The analog multiplexer multiplexes the digital amplitude signal with the differential bias signal in parallel and generates a first differential signal. A driver module receives the first differential signal and a second differential signal. The driver module generates a first drive signal proportional to the dynamic power control signal when a bit in said digital amplitude signal is a logic one and the driver module generates a second drive signal proportional to the second differential signal when a bit in said digital amplitude signal is a logic zero.

    摘要翻译： 功率控制模块接收动态功率控制信号并产生与动态功率控制信号成比例的差分偏置信号。 模拟多路复用器接收包括n位的数字幅度信号并接收差分偏置信号。 模拟多路复用器将数字幅度信号与差分偏置信号并行复用，并产生第一差分信号。 驱动器模块接收第一差分信号和第二差分信号。 当所述数字幅度信号中的位为逻辑1时，驱动器模块产生与动态功率控制信号成比例的第一驱动信号，并且当所述数字幅度信号中的位为逻辑1时，驱动器模块产生与第二差分信号成比例的第二驱动信号 是逻辑0。

    Differential analog filter
    2.
    发明申请
    Differential analog filter 审中-公开
    差分模拟滤波器

    公开(公告)号：US20060255997A1

    公开(公告)日：2006-11-16

    申请号：US11398286

    申请日：2006-04-04

    申请人： Chin Li ,  Paul Sheehy ,  Eoin Carey ,  Gerard Quilligan ,  Walid Mohamed Ahmed

    发明人： Chin Li ,  Paul Sheehy ,  Eoin Carey ,  Gerard Quilligan ,  Walid Mohamed Ahmed

    IPC分类号： H03M1/12

    CPC分类号： H04W52/52 ,  H03F1/26 ,  H03F3/211 ,  H03F3/24 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/331 ,  H03F2203/45356 ,  H03H11/1291 ,  H03H11/245 ,  H03M1/0854 ,  H03M1/66

    摘要： A differential analog filter includes a differential input that includes a first input node and a second input node and a differential output that includes a first output node and a second output node. A fully differential amplifier includes a non-inverting input node and an inverting input node coupled to the differential input. The fully differential amplifier includes a non-inverting output node and an inverting output node coupled to the differential output. A first feedback network is coupled between the non-inverting output node and the inverting input node of the fully differential amplifier. A second feedback network is coupled between the inverting output node and the non-inverting input node of the fully differential amplifier.

    摘要翻译： 差分模拟滤波器包括包括第一输入节点和第二输入节点的差分输入以及包括第一输出节点和第二输出节点的差分输出。 全差分放大器包括非反相输入节点和耦合到差分输入的反相输入节点。 全差分放大器包括非反相输出节点和耦合到差分输出的反相输出节点。 第一反馈网络耦合在非反相输出节点和全差分放大器的反相输入节点之间。 第二反馈网络耦合在全差分放大器的反相输出节点和非反相输入节点之间。

    Sub-ranging digital to analog converter for radiofrequency amplification
    3.
    发明申请
    Sub-ranging digital to analog converter for radiofrequency amplification 失效
    用于射频放大的子范围数模转换器

    公开(公告)号：US20060049971A1

    公开(公告)日：2006-03-09

    申请号：US10935952

    申请日：2004-09-08

    申请人： Gerard Quilligan ,  Pierce Nagle ,  Eugene Heaney

    发明人： Gerard Quilligan ,  Pierce Nagle ,  Eugene Heaney

    IPC分类号： H03M1/66

    CPC分类号： H03M1/68 ,  H03M1/745

    摘要： An apparatus and method for amplifying a radiofrequency signal using a main Digital to Analog Converter (RFDAC) and a subordinate Digital to Analog Converter (Sub-DAC). The main RFDAC provides a first portion of a N-bit digital output, which specifies the amplification level of the radiofrequency signal, and the sub-DAC provides a second portion of the N-bit digital word. Together, the main RFDAC and the Sub-DAC convert a complete N-bit digital word, where N specifies the resolution of the output radiofrequency signal.

    摘要翻译： 一种用于使用主数模转换器（RFDAC）和从属数模转换器（Sub-DAC）放大射频信号的装置和方法。 主RFDAC提供N位数字输出的第一部分，其指定射频信号的放大电平，并且子DAC提供N位数字字的第二部分。 一起，主RFDAC和子DAC转换一个完整的N位数字字，其中N指定输出射频信号的分辨率。

    Piecewise linearizer circuit for radio frequency amplification
    5.
    发明申请
    Piecewise linearizer circuit for radio frequency amplification 失效
    用于射频放大的分段线性化电路

    公开(公告)号：US20060229037A1

    公开(公告)日：2006-10-12

    申请号：US11095069

    申请日：2005-03-31

    申请人： Gerard Quilligan

    发明人： Gerard Quilligan

    IPC分类号： H04B1/04 ,  H04B1/02

    CPC分类号： H03F1/3241

    摘要： An apparatus and method for amplifying a radio frequency signal including, generating a plurality of shaped pulses utilizing a piecewise linearizer circuit, applying the plurality of shaped pulses to a first input of a radio frequency amplifier circuit, and injecting a radio frequency carrier into a second input of the radio frequency amplifier circuit. The apparatus comprises a piecewise linearizer (PWL) circuit coupled to the input of a Radio Frequency Digital to Analog Converter (RFDAC) operating as a signal amplifier.

    摘要翻译： 一种用于放大射频信号的装置和方法，包括利用分段线性化电路产生多个成形脉冲，将多个成形脉冲施加到射频放大器电路的第一输入端，以及将射频载波注入第二个 输入射频放大电路。 该装置包括耦合到作为信号放大器工作的射频数模转换器（RFDAC）的输入端的分段线性化电路（PWL）电路。