公开(公告)号：US20150303246A1

公开(公告)日：2015-10-22

申请号：US14297008

申请日：2014-06-05

Applicant: Cirrus Logic, Inc.

Inventor： Zhonghai Shi ,  Vince Deems ,  Hong Tian

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/32055 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649

Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.

Abstract translation: 根据本公开的实施例，集成电路可以包括浅沟槽隔离场氧化物的至少一个区域，至少一个虚拟扩散区域和多晶半导体电阻器。 浅沟槽隔离场氧化物的至少一个区域可以形成在半导体衬底上。 可以在半导体衬底上的浅沟槽隔离场氧化物的至少一个区域附近形成虚拟扩散的至少一个区域。 多晶半导体电阻器可以包括形成有多晶半导体材料的至少一个电阻臂，其中至少一个电阻臂形成在浅沟槽隔离场氧化物的至少一个区域中的每一个上，并且虚拟的至少一个区域 扩散。

公开(公告)号：US10068779B2

公开(公告)日：2018-09-04

申请号：US15675242

申请日：2017-08-11

Applicant: Cirrus Logic, Inc.

Inventor： Zhonghai Shi ,  Vince Deems ,  Hong Tian

IPC: H01L21/32 ,  H01L21/3205 ,  H01L21/763 ,  H01L49/02 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08

Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.

公开(公告)号：US09761461B2

公开(公告)日：2017-09-12

申请号：US14297008

申请日：2014-06-05

Applicant: Cirrus Logic, Inc.

Inventor： Zhonghai Shi ,  Vince Deems ,  Hong Tian

IPC: H01L29/06 ,  H01L21/3205 ,  H01L21/762 ,  H01L27/08 ,  H01L49/02 ,  H01L21/763

CPC classification number: H01L21/32055 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649

Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.