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公开(公告)号：US09678669B2
公开(公告)日：2017-06-13
申请号：US14083437
申请日：2013-11-18
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
IPC: G06F17/50 , G06F9/455 , G06F3/06 , G06F12/0844 , G06F12/0846 , G06F12/0855
CPC classification number: G06F3/0607 , G06F3/0629 , G06F3/0683 , G06F12/0844 , G06F12/0851 , G06F12/0855
Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.
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公开(公告)号：US09466395B2
公开(公告)日：2016-10-11
申请号：US14856758
申请日：2015-09-17
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Shadab Nazar , Sanjeev Joshi
CPC classification number: G11C29/12 , G11C29/08 , G11C29/56008 , G11C29/70 , G11C2029/0401 , G11C2029/0409
Abstract: An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.
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Patent Agency Ranking
公开(公告)号：US20160179394A1
公开(公告)日：2016-06-23
申请号：US14083437
申请日：2013-11-18
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
IPC: G06F3/06
CPC classification number: G06F3/0607 , G06F3/0629 , G06F3/0683 , G06F12/0844 , G06F12/0851 , G06F12/0855
Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.
Abstract translation: 为集成电路设计存储器子系统可能是耗时且昂贵的任务。 为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。 自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。 潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。 满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。 当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及用于存储器系统的测试套件。
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4.发明申请公开(公告)号：US20160005493A1
公开(公告)日：2016-01-07
申请号：US14856758
申请日：2015-09-17
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Shadab Nazar , Sanjeev Joshi
IPC: G11C29/12
CPC classification number: G11C29/12 , G11C29/08 , G11C29/56008 , G11C29/70 , G11C2029/0401 , G11C2029/0409
Abstract: An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.
Abstract translation: 公开了用于存储器的ActiveTest解决方案，其可以在包含数字存储器的产品的操作期间搜索存储器错误。 ActiveTest系统测试正常内存用户未被访问的内存块，以便在后台持续测试内存系统。 当ActiveTest系统和内存用户之间存在冲突时，内存用户通常被优先考虑。
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5.发明授权公开(公告)号：US09165687B2
公开(公告)日：2015-10-20
申请号：US14160542
申请日：2014-01-21
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Shadab Nazar , Sanjeev Joshi
CPC classification number: G11C29/12 , G11C29/08 , G11C29/56008 , G11C29/70 , G11C2029/0401 , G11C2029/0409
Abstract: An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.
Abstract translation: 公开了用于存储器的ActiveTest解决方案，其可以在包含数字存储器的产品的操作期间搜索存储器错误。 ActiveTest系统测试正常内存用户未被访问的内存块，以便在后台持续测试内存系统。 当ActiveTest系统和内存用户之间存在冲突时，内存用户通常被优先考虑。
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公开(公告)号：US09390212B2
公开(公告)日：2016-07-12
申请号：US14702971
申请日：2015-05-04
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC: G11C11/00 , G06F17/50 , G11C11/419
CPC classification number: G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
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公开(公告)号：US20150234950A1
公开(公告)日：2015-08-20
申请号：US14702971
申请日：2015-05-04
Applicant: Cisco Technology, Inc.
Inventor： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC: G06F17/50 , G11C11/419
CPC classification number: G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
Abstract translation: 现代数字集成电路中通常需要多端口存储器电路来存储数据。 多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。 多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。 然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。 公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。
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