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252 条记录 (耗时 0.026 秒)

    Lock-free ring buffer
    1.
    发明授权
    Lock-free ring buffer 有权

    公开(公告)号：US11886343B2

    公开(公告)日：2024-01-30

    申请号：US17454475

    申请日：2021-11-10

    申请人： DreamWorks Animation LLC

    发明人： Keith Jeffery

    IPC分类号： G06F12/0815 ,  G06F12/0844

    CPC分类号： G06F12/0815 ,  G06F12/0844 ,  G06F2212/1041

    摘要： According to at least one embodiment, a method for writing, by a computing thread, data to a ring buffer is disclosed. The method includes determining whether the ring buffer is full. If the ring buffer is not full, the method further includes: reserving an element of the ring buffer for writing the data, wherein reserving the element includes incrementing a size variable corresponding to a number of stored elements in the ring buffer; reserving a portion of the ring buffer at which the data is to be written; and determining whether a state of the portion of the ring buffer is in change by at least one other computing thread. If the state is not in change, the method further includes: marking the state of the portion of the ring buffer as being in change by the computing thread; and writing the data to the portion of the ring buffer.

    Storage device performing cache read operation using page buffer and operating method thereof
    2.
    发明授权
    Storage device performing cache read operation using page buffer and operating method thereof 有权

    公开(公告)号：US11734178B2

    公开(公告)日：2023-08-22

    申请号：US17358922

    申请日：2021-06-25

    申请人： SK hynix Inc.

    发明人： Chung Un Na

    IPC分类号： G06F12/08 ,  G06F12/0844 ,  G06F12/02

    CPC分类号： G06F12/0844 ,  G06F12/0253 ,  G06F2212/608 ,  G06F2212/7205

    摘要： A storage device includes: a memory device including a plurality of planes, and a plurality of cache buffers and data buffers; and a memory controller for controlling the memory device to transmit first data and second data from first plane and second plane into the respective first cache buffer and second cache buffer, and control the first cache buffer and the second cache buffer to transmit the first data and the second data to the memory controller. In response to a read request for third data from a host while the first data is transmitting from the first cache buffer to the memory controller, the memory controller transmits a cache read command to the memory device such that the memory device reads the third data after the first data is completely transmitted to the memory controller, before the second data is transmitted from the second cache buffer.

    ARITHMETIC PROCESSING UNIT, MEMORY ACCESS CONTROLLER, AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT
    5.
    发明申请
    ARITHMETIC PROCESSING UNIT, MEMORY ACCESS CONTROLLER, AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT 审中-公开

    公开(公告)号：US20190188139A1

    公开(公告)日：2019-06-20

    申请号：US16199294

    申请日：2018-11-26

    申请人： FUJITSU LIMITED

    发明人： Kodai MORITAKA

    IPC分类号： G06F12/0844

    CPC分类号： G06F12/0844 ,  G06F2212/1016

    摘要： An arithmetic processing unit includes a processing unit, a cache control unit that issues a request for the memory access, and a memory access controller that includes a request queue, and a request selection unit which selects a request from among requests enqueued in the request queue and issues the selected request to a memory. After issue of a previous request in the request queue, the request selection unit inhibits, during an issue inhibition period corresponding to the issued previous request, issue of a subsequent request corresponding to the issue inhibition period, and the request selection unit issues a second request in preference to a first request in a case where the requests in the request queue are in a first state, the first request being one of a read request and a write request in the request queue, and the second request being a request in the request queue.