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1.发明授权Contact base with detachable contacts for making electrical contact with an electronic component, in particular a multipin electronic component, and module carrier 有权接触基座具有用于与电子部件，特别是多功能电子部件和模块载体电接触的可拆卸触点公开(公告)号：US06840778B2
公开(公告)日：2005-01-11
申请号：US10340464
申请日：2003-01-10
申请人： Claus Engelhardt , Jörg Kliewer , Rupert Lukas , Jan Spitz
发明人： Claus Engelhardt , Jörg Kliewer , Rupert Lukas , Jan Spitz
CPC分类号： G01R1/0466 , H01R12/7076 , H01R2201/20 , H05K7/1023
摘要： A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic conditions in a real application environment. In practice, such components are normally firmly soldered in on a module carrier. Owing to the thermal load during soldering, this solution cannot always be used and, furthermore, the contacts that are made should be detachable. Commercially available contact bases with detachable contacts cannot be used, however, since their dimensions are too large and they do not fit in the available surface area on the module carrier. The novel contact base is sufficiently small that a plurality of contact bases can be arranged closely one next to the other in a row in a very small space on a module carrier. The module carrier has plug contacts to be plugged into a commercial socket in order to make contact.
摘要翻译： 特别是关于存储器组件分析的频繁问题是存储器组件必须在实际应用环境中的现实条件下进行测试。 实际上，这些组件通常牢固地焊接在模块载体上。 由于焊接时的热负荷，该溶液不能总是被使用，此外，制成的触点应该是可拆卸的。 不可以使用具有可拆卸接触件的市售接触基座，但是由于它们的尺寸太大并且它们不适合于模块载体上的可用表面积。 新颖的接触基底足够小，使得多个接触基底可以在模块载体上的非常小的空间中彼此紧邻地布置成一排。 模块托架具有插头接头以插入商业插座以便接触。
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2.发明授权公开(公告)号：US06781889B2
公开(公告)日：2004-08-24
申请号：US10247572
申请日：2002-09-19
申请人： Jörg Kliewer , Rupert Lukas , Manfred Pröll , Stephan Schröder
发明人： Jörg Kliewer , Rupert Lukas , Manfred Pröll , Stephan Schröder
IPC分类号： G11C1604
CPC分类号： G11C29/34 , G11C29/26 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： An additional test mode is introduced in a semiconductor memory. A multiplicity of word lines are simultaneously activated by a word line decoder in the test mode. After a potential equalization of complementary bit lines, a logic “0” or a logic “1” is applied to an equalization circuit via a voltage generator. It is thus possible for the entire memory cell array to be preallocated an identical data value or, in strip form, alternating data values. Test time is thereby saved.
摘要翻译： 在半导体存储器中引入另外的测试模式。 在测试模式下，字线解码器同时激活多条字线。 在互补位线的电位均衡之后，通过电压发生器将逻辑“0”或逻辑“1”施加到均衡电路。 因此，可以将整个存储单元阵列预先分配相同的数据值，或者以带状形式预分配交替的数据值。 从而节省测试时间。
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