公开(公告)号：US07236412B2

公开(公告)日：2007-06-26

申请号：US11053659

申请日：2005-02-09

申请人： Manfred Pröll ,  Johann Pfeiffer ,  Stephan Schröder ,  Arndt Gruber ,  Georg Erhard Eggers

发明人： Manfred Pröll ,  Johann Pfeiffer ,  Stephan Schröder ,  Arndt Gruber ,  Georg Erhard Eggers

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C7/1006 ,  G11C11/401 ,  G11C29/36 ,  G11C29/50016 ,  G11C29/80

摘要： An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

摘要翻译： 一种集成半导体存储器，包括可以经由第一和第二字线驱动并可由冗余存储器单元代替的存储单元。 在第一存储单元类型中，可以对应于存在于数据输入端的数据存储数据。 在第二存储单元类型的存储单元中，数据可以相对于存在于数据输入端的数据反转存储。 集成半导体存储器包括用于数据反转的电路，其中数据被写入冗余存储单元，相对于存在于数据输入端的数据而被反转，如果有缺陷的存储单元和替换它的冗余存储单元位于不同的 位线的字线条扭曲，并且如果不良存储器单元和替换它的冗余存储器单元与不同的存储器单元类型相关联。

公开(公告)号：US07206980B2

公开(公告)日：2007-04-17

申请号：US11123221

申请日：2005-05-06

申请人： Jürgen Auge ,  Manfred Pröll ,  Jörg Kliewer ,  Frank Schroeppel

发明人： Jürgen Auge ,  Manfred Pröll ,  Jörg Kliewer ,  Frank Schroeppel

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/48

摘要： An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

摘要翻译： 集成半导体存储器包括具有存储有数据值的至少一个存储单元的存储单元阵列和具有计数器的评估电路。 在集成半导体存储器的测试期间，如果存储在存储单元中的数据值偏离期望值，则计数器的计数器读数被改变。 阈值由控制电路预先定义。 编程电路将输入侧的阈值与计数器的瞬时计数器读数进行比较。 如果计数器的计数器读数超过阈值，则编程元件从第一编程状态变为第二编程状态。 在测试结束之后，通过输出端读出编程元件的状态。 该方案可以推断集成半导体存储器的可能的故障原因。

公开(公告)号：US06992498B2

公开(公告)日：2006-01-31

申请号：US10791768

申请日：2004-03-04

申请人： Manfred Pröll ,  Gerrit Färber

发明人： Manfred Pröll ,  Gerrit Färber

IPC分类号： G01R31/28

CPC分类号： G11C29/56 ,  G01R31/2855 ,  G01R31/318505 ,  G11C2029/2602

摘要： A test apparatus for testing integrated modules has a plurality of connection locations on a carrier substrate. An integrated module may be connected, via a connection location, to a test unit connected to the carrier substrate. The connection locations are arranged in groups within a connection array. A control terminal via which an integrated module may be selected for a test can be provided for each connection location. An address and command terminal can be provided for each connection location. The modules of the number of groups, which are simultaneously operated, are connected to the address and command bus via the respective switching means or switch. The test frequency can thus be increased without adversely affecting the driver load.

摘要翻译： 用于测试集成模块的测试装置在载体基板上具有多个连接位置。 集成模块可以经由连接位置连接到连接到载体衬底的测试单元。 连接位置在连接阵列内分组排列。 可以为每个连接位置提供可以选择用于测试的集成模块的控制终端。 可以为每个连接位置提供地址和命令终端。 同时操作的组数的模块通过相应的开关装置或开关连接到地址和命令总线。 因此可以增加测试频率，而不会不利地影响驾驶员负载。

公开(公告)号：US20050281118A1

公开(公告)日：2005-12-22

申请号：US11140554

申请日：2005-05-27

申请人： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

发明人： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

IPC分类号： G11C8/00 ,  G11C8/08 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C11/4085 ,  G11C29/02 ,  G11C29/025 ,  G11C29/83 ,  G11C29/832 ,  G11C2029/1202 ,  H01L27/10891 ,  H01L27/10897

摘要： An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

摘要翻译： 集成半导体存储器包括至少一个字线和多个存储器单元。 每个存储单元具有耦合到字线的选择晶体管。 字线驱动器耦合到字线。 字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。 无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。 无源元件对于字线和触点连接之间的漏电流是透射的。

公开(公告)号：US06940775B2

公开(公告)日：2005-09-06

申请号：US10823608

申请日：2004-04-14

申请人： Ralf Schneider ,  Manfred Pröll ,  Georg Erhard Eggers ,  Jörg Kliewer

发明人： Ralf Schneider ,  Manfred Pröll ,  Georg Erhard Eggers ,  Jörg Kliewer

IPC分类号： G11C8/02 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C2211/4061

摘要： An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

摘要翻译： 集成动态存储器包括被组合以形成单独的可独立寻址单元的存储单元，以及用于控制存储器单元的刷新模式的控制电路。 存储单元可以刷新其存储单元格内容。 控制电路被设计成使得一个或多个单元的存储单元可以在更新周期中并行进行刷新模式。 控制电路基于温度参考值设置要在刷新周期中并行刷新的多个存储单元单元。 可以增加存储器芯片的最大可能工作温度，而不需要对存储器访问的额外限制。

公开(公告)号：US07266027B2

公开(公告)日：2007-09-04

申请号：US11235540

申请日：2005-09-27

申请人： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Herbert Benzinger

发明人： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Herbert Benzinger

IPC分类号： G11C7/00

CPC分类号： G11C29/025 ,  G11C8/08 ,  G11C11/401 ,  G11C29/02 ,  G11C2029/1202

摘要： An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

摘要翻译： 集成半导体存储器包括通过相应的第一可控开关和相应的第三可控开关连接到第一电压电位的字线，以及经由相应的第二可控开关连接到第二电压电位的字线。 为了测试字线之一是否经由其相应的第一和第三可控开关连接到第一电压电位，所述字线之一经由相应的第二可控开关和驱动器线连接到比较器电路。 在相应的第一和第三可控开关已经被控制为导通状态之后，在集成半导体存储器的测试操作状态下，将相应的第二可控开关控制在导通状态，并且字线上的电位状态由 比较器电路。 评估结果通过评估信号馈送到外部数据终端。

公开(公告)号：US07251772B2

公开(公告)日：2007-07-31

申请号：US10732402

申请日：2003-12-11

申请人： Christian Stocken ,  Gerald Resch ,  Manfred Pröll ,  Manfred Dobler

发明人： Christian Stocken ,  Gerald Resch ,  Manfred Pröll ,  Manfred Dobler

IPC分类号： G06F11/08 ,  G06F13/14

CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/02 ,  G11C29/1201 ,  G11C2029/5006

摘要： A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

摘要翻译： 电路装置可以具有多个集成电路部件，其被布置在载体基板上。 用于接收控制信号的接收电路可以耦合到输入侧的一个连接焊盘，并且可以连接到输出侧的每个电路部件。 由测试模式信号控制的桥接电路可以使接收电路电桥。 在测试方法中，多个连接焊盘可以连接到第一电位，并且至少一个连接焊盘可以连接到第二电位。 可以激活桥接电路，并且通过测试装置在至少一个连接焊盘处测量电流。 可以测量输入侧接收电路和电路部件之间的连接中的漏电流的检查。

公开(公告)号：US06999355B2

公开(公告)日：2006-02-14

申请号：US10841546

申请日：2004-05-10

申请人： Herbert Benzinger ,  Koen Van der Zanden ,  Stephan Schröder ,  Manfred Pröll

发明人： Herbert Benzinger ,  Koen Van der Zanden ,  Stephan Schröder ,  Manfred Pröll

IPC分类号： G11C7/00 ,  G11C7/04

CPC分类号： G11C11/4091 ,  G11C5/14 ,  G11C7/06 ,  G11C2207/065

摘要： A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.

摘要翻译： 用于设置用于集成存储器的读/写放大器的电压源的电路装置具有第一电压发生器电路，用于在评估和放大操作期间产生用于施加到读/写放大器的电源电压，以及第二电压发生器电路， 产生用于对连接到读/写放大器的存储器的位线进行预充电的预充电电压。 连接到第一电压发生器电路的温度检测器电路用于检测存储器的温度并与第一电压发生器电路相互作用以将施加到读/写放大器的电源电压设置为取决于 记忆温度

公开(公告)号：US07181579B2

公开(公告)日：2007-02-20

申请号：US10798334

申请日：2004-03-12

申请人： Aurel von Campenhausen ,  Manfred Pröll ,  Jörg Kliewer ,  Stephan Schröder

发明人： Aurel von Campenhausen ,  Manfred Pröll ,  Jörg Kliewer ,  Stephan Schröder

IPC分类号： G06F12/16 ,  G11C11/413

CPC分类号： G11C29/44 ,  G11C29/78 ,  G11C2029/4402

摘要： An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

摘要翻译： 集成存储器具有可单独寻址的存储器单元的正常和冗余单元。 存储单元用于以正常模式存储需要由冗余单元之一替代的正常单元之一的地址。 比较单元将存在于地址总线上的地址与存储在存储器单元中的地址进行比较，并且在匹配被识别的情况下激活冗余单元中的一个。 存储器还具有可由测试模式信号激活的测试电路，可以将存储器单元重置为初始状态，并且可以将存储器单元中的一个冗余单元的地址存储在随后向其中写入识别码 冗余单元。

公开(公告)号：US07102912B2

公开(公告)日：2006-09-05

申请号：US11071590

申请日：2005-03-04

申请人： Herbert Benzinger ,  Jörg Kliewer ,  Manfred Pröll ,  Stephan Schröder

发明人： Herbert Benzinger ,  Jörg Kliewer ,  Manfred Pröll ,  Stephan Schröder

IPC分类号： G11C11/00

CPC分类号： G11C11/4094 ,  G11C7/02 ,  G11C7/12

摘要： An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

摘要翻译： 集成半导体存储器件包括具有第一位线和第二位线（BL，/ BL）的存储单元阵列（B 1），可控电阻器（SW）和控制单元（100），其被配置为控制可控电阻器 。 在集成半导体存储器件的第一操作状态下，第一和第二位线经由第一可控开关（ET 1）彼此连接，并且还经由设置为低电阻的可控电阻（SW）连接， 涉及施加中间电压（V BAT）的连接（A 10），其中中压的电压电平为第一和第二电压电位之间的算术平均值 VBLH，VBLL）。 由于控制单元在集成半导体存储器件的第一操作状态下将可控电阻短暂地设置为非常低的电阻，所以第一和第二位线所需的时间段需要采用中间电压（V < SUB> BLEQ ）缩短。 因此，将第一和第二位线的充电速度降低到中间电压的电容耦合影响的影响显着减小。