公开(公告)号：US06840778B2

公开(公告)日：2005-01-11

申请号：US10340464

申请日：2003-01-10

Applicant: Claus Engelhardt ,  Jörg Kliewer ,  Rupert Lukas ,  Jan Spitz

Inventor： Claus Engelhardt ,  Jörg Kliewer ,  Rupert Lukas ,  Jan Spitz

IPC: G01R1/04 ,  H01R12/70 ,  H05K7/10 ,  H01R12/00

CPC classification number: G01R1/0466 ,  H01R12/7076 ,  H01R2201/20 ,  H05K7/1023

Abstract: A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic conditions in a real application environment. In practice, such components are normally firmly soldered in on a module carrier. Owing to the thermal load during soldering, this solution cannot always be used and, furthermore, the contacts that are made should be detachable. Commercially available contact bases with detachable contacts cannot be used, however, since their dimensions are too large and they do not fit in the available surface area on the module carrier. The novel contact base is sufficiently small that a plurality of contact bases can be arranged closely one next to the other in a row in a very small space on a module carrier. The module carrier has plug contacts to be plugged into a commercial socket in order to make contact.

Abstract translation: 特别是关于存储器组件分析的频繁问题是存储器组件必须在实际应用环境中的现实条件下进行测试。 实际上，这些组件通常牢固地焊接在模块载体上。 由于焊接时的热负荷，该溶液不能总是被使用，此外，制成的触点应该是可拆卸的。 不可以使用具有可拆卸接触件的市售接触基座，但是由于它们的尺寸太大并且它们不适合于模块载体上的可用表面积。 新颖的接触基底足够小，使得多个接触基底可以在模块载体上的非常小的空间中彼此紧邻地布置成一排。 模块托架具有插头接头以插入商业插座以便接触。

公开(公告)号：US06781889B2

公开(公告)日：2004-08-24

申请号：US10247572

申请日：2002-09-19

Applicant: Jörg Kliewer ,  Rupert Lukas ,  Manfred Pröll ,  Stephan Schröder

Inventor： Jörg Kliewer ,  Rupert Lukas ,  Manfred Pröll ,  Stephan Schröder

IPC: G11C1604

CPC classification number: G11C29/34 ,  G11C29/26 ,  G11C2029/1204 ,  G11C2029/1802 ,  G11C2029/2602

Abstract: An additional test mode is introduced in a semiconductor memory. A multiplicity of word lines are simultaneously activated by a word line decoder in the test mode. After a potential equalization of complementary bit lines, a logic “0” or a logic “1” is applied to an equalization circuit via a voltage generator. It is thus possible for the entire memory cell array to be preallocated an identical data value or, in strip form, alternating data values. Test time is thereby saved.

Abstract translation: 在半导体存储器中引入另外的测试模式。 在测试模式下，字线解码器同时激活多条字线。 在互补位线的电位均衡之后，通过电压发生器将逻辑“0”或逻辑“1”施加到均衡电路。 因此，可以将整个存储单元阵列预先分配相同的数据值，或者以带状形式预分配交替的数据值。 从而节省测试时间。

公开(公告)号：US06859406B2

公开(公告)日：2005-02-22

申请号：US10724906

申请日：2003-12-01

Applicant: Manfred Pröll ,  Stephan Schröder ,  Claus Engelhardt ,  Jörg Kliewer

Inventor： Manfred Pröll ,  Stephan Schröder ,  Claus Engelhardt ,  Jörg Kliewer

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/24 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4076 ,  G11C11/4094

Abstract: A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are connected in pairs from two adjacent blocks in each case to a common sense amplifier and the sense amplifiers are disposed between the cell blocks. In which case bit line switches are disposed in sense amplifier strips—lying between the blocks—between in each case two adjacent sense amplifiers in order to momentarily connect the other ends—not connected to the sense amplifiers—of two bit line pairs from the adjacent cell blocks during a precharge phase of a bit line pair activated directly beforehand. The precharge phase takes place at the start of a charge equalization phase.

Abstract translation: 具有共享读出放大器组织概念的动态RAM半导体存储器，其中单元阵列被细分为块，其位线在每种情况下从两个相邻块成对连接到公共读出放大器，并且读出放大器设置在单元之间 块。 在哪种情况下，位线开关设置在位于块之间的读出放大器条中 - 在每种情况下在两个相邻的读出放大器之间，以便将来自相邻的两个位线对的未连接到读出放大器的另一端 在预先激活的位线对的预充电阶段期间的单元块。 预充电阶段在充电均衡阶段开始时进行。

公开(公告)号：US07428673B2

公开(公告)日：2008-09-23

申请号：US11214482

申请日：2005-08-29

Applicant: Jörg Kliewer ,  Martin Versen

Inventor： Jörg Kliewer ,  Martin Versen

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/02 ,  G11C5/04 ,  G11C29/025

Abstract: The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

Abstract translation: 本发明涉及一种用于确定具有布置在其上的至少一个部件的电路载体的导线配置的测试方法，其中部件中的内部线以规定的顺序连接到部件连接，并且其中部件连接被连接到 电路载体。 根据该方法，使用集成在该部件中的可控测试信号发生器将各个规定的测试信号施加到部件的每条内部线路。 施加到电路载体的连接的输出信号被分接。 此后，使用用于确定部件连接和电路载体连接之间的导线配置的外部测试装置，利用施加到部件的内部线路的相应测试信号来识别各个输出信号。

公开(公告)号：US07443713B2

公开(公告)日：2008-10-28

申请号：US11331365

申请日：2006-01-13

Applicant: Stephan Schröder ,  Herbert Benzinger ,  Georg Erhard Eggers ,  Manfred Pröll ,  Jörg Kliewer

Inventor： Stephan Schröder ,  Herbert Benzinger ,  Georg Erhard Eggers ,  Manfred Pröll ,  Jörg Kliewer

IPC: G11C11/02

CPC classification number: G11C11/404 ,  H01L27/10885

Abstract: An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Abstract translation: 集成半导体存储器件包括至少一个存储器单元，至少一个读出放大器和连接到每个读出放大器的一对位线，其中每个存储器单元包括选择晶体管和存储电容器。 每个存储单元的存储电容器包括第一电容器电极和第二电容器电极，并且每个存储单元的选择晶体管包括通过第一接触连接连接到一对位的一个位线的第一源极/漏极区域 与存储单元相对应的线，以及与存储单元的存储电容器的第一电容电极导电连接的第二源/漏区。 每个存储单元的存储电容器的第二电容器电极连接到与存储单元相对应的一对位线的另一位线。

公开(公告)号：US07180820B2

公开(公告)日：2007-02-20

申请号：US11140554

申请日：2005-05-27

Applicant: Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

Inventor： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

IPC: G11C8/00

CPC classification number: G11C11/4085 ,  G11C29/02 ,  G11C29/025 ,  G11C29/83 ,  G11C29/832 ,  G11C2029/1202 ,  H01L27/10891 ,  H01L27/10897

Abstract: An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Abstract translation: 集成半导体存储器包括至少一个字线和多个存储器单元。 每个存储单元具有耦合到字线的选择晶体管。 字线驱动器耦合到字线。 字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。 无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。 无源元件对于字线和触点连接之间的漏电流是透射的。

公开(公告)号：US07196572B2

公开(公告)日：2007-03-27

申请号：US11123226

申请日：2005-05-06

Applicant: Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Jörg Kliewer

Inventor： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Jörg Kliewer

IPC: G05F1/10

CPC classification number: G11C11/4074 ,  G11C5/145

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Abstract translation: 集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。 包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。 控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值 输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。 结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。

公开(公告)号：US07158426B2

公开(公告)日：2007-01-02

申请号：US11121175

申请日：2005-05-04

Applicant: Koen van der Zanden ,  Manfred Pröll ,  Jörg Kliewer ,  Björn Wirker

Inventor： Koen van der Zanden ,  Manfred Pröll ,  Jörg Kliewer ,  Björn Wirker

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C29/12015 ,  G11C29/50012 ,  G11C2029/1204 ,  G11C2029/2602

Abstract: An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

Abstract translation: 集成半导体存储器可以在与控制时钟同步的正常操作状态下操作。 在测试操作状态下，集成半导体存储器与第一控制信号的控制时钟的时钟边沿同步地驱动，并独立于控制时钟启动测试运行。 利用第一控制信号驱动，可以由存储体地址选择的存储体中的选择晶体管截止。 之后，所选择的存储体中的位线被互连并以预定的预充电势驱动。 在预充电时间过去之后，通过应用的字线地址选择一个字线，并且连接到所选字线的所选存储体中的选择晶体管导通。 独立于控制时钟的时钟周期设置和测试预充电时间。

公开(公告)号：US07181579B2

公开(公告)日：2007-02-20

申请号：US10798334

申请日：2004-03-12

Applicant: Aurel von Campenhausen ,  Manfred Pröll ,  Jörg Kliewer ,  Stephan Schröder

Inventor： Aurel von Campenhausen ,  Manfred Pröll ,  Jörg Kliewer ,  Stephan Schröder

IPC: G06F12/16 ,  G11C11/413

CPC classification number: G11C29/44 ,  G11C29/78 ,  G11C2029/4402

Abstract: An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Abstract translation: 集成存储器具有可单独寻址的存储器单元的正常和冗余单元。 存储单元用于以正常模式存储需要由冗余单元之一替代的正常单元之一的地址。 比较单元将存在于地址总线上的地址与存储在存储器单元中的地址进行比较，并且在匹配被识别的情况下激活冗余单元中的一个。 存储器还具有可由测试模式信号激活的测试电路，可以将存储器单元重置为初始状态，并且可以将存储器单元中的一个冗余单元的地址存储在随后向其中写入识别码 冗余单元。

公开(公告)号：US07102912B2

公开(公告)日：2006-09-05

申请号：US11071590

申请日：2005-03-04

Applicant: Herbert Benzinger ,  Jörg Kliewer ,  Manfred Pröll ,  Stephan Schröder

Inventor： Herbert Benzinger ,  Jörg Kliewer ,  Manfred Pröll ,  Stephan Schröder

IPC: G11C11/00

CPC classification number: G11C11/4094 ,  G11C7/02 ,  G11C7/12

Abstract: An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

Abstract translation: 集成半导体存储器件包括具有第一位线和第二位线（BL，/ BL）的存储单元阵列（B 1），可控电阻器（SW）和控制单元（100），其被配置为控制可控电阻器 。 在集成半导体存储器件的第一操作状态下，第一和第二位线经由第一可控开关（ET 1）彼此连接，并且还经由设置为低电阻的可控电阻（SW）连接， 涉及施加中间电压（V BAT）的连接（A 10），其中中压的电压电平为第一和第二电压电位之间的算术平均值 VBLH，VBLL）。 由于控制单元在集成半导体存储器件的第一操作状态下将可控电阻短暂地设置为非常低的电阻，所以第一和第二位线所需的时间段需要采用中间电压（V < SUB> BLEQ ）缩短。 因此，将第一和第二位线的充电速度降低到中间电压的电容耦合影响的影响显着减小。