公开(公告)号：US07443713B2

公开(公告)日：2008-10-28

申请号：US11331365

申请日：2006-01-13

申请人： Stephan Schröder ,  Herbert Benzinger ,  Georg Erhard Eggers ,  Manfred Pröll ,  Jörg Kliewer

发明人： Stephan Schröder ,  Herbert Benzinger ,  Georg Erhard Eggers ,  Manfred Pröll ,  Jörg Kliewer

IPC分类号： G11C11/02

CPC分类号： G11C11/404 ,  H01L27/10885

摘要： An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

摘要翻译： 集成半导体存储器件包括至少一个存储器单元，至少一个读出放大器和连接到每个读出放大器的一对位线，其中每个存储器单元包括选择晶体管和存储电容器。 每个存储单元的存储电容器包括第一电容器电极和第二电容器电极，并且每个存储单元的选择晶体管包括通过第一接触连接连接到一对位的一个位线的第一源极/漏极区域 与存储单元相对应的线，以及与存储单元的存储电容器的第一电容电极导电连接的第二源/漏区。 每个存储单元的存储电容器的第二电容器电极连接到与存储单元相对应的一对位线的另一位线。

公开(公告)号：US07180820B2

公开(公告)日：2007-02-20

申请号：US11140554

申请日：2005-05-27

申请人： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

发明人： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

IPC分类号： G11C8/00

CPC分类号： G11C11/4085 ,  G11C29/02 ,  G11C29/025 ,  G11C29/83 ,  G11C29/832 ,  G11C2029/1202 ,  H01L27/10891 ,  H01L27/10897

摘要： An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

摘要翻译： 集成半导体存储器包括至少一个字线和多个存储器单元。 每个存储单元具有耦合到字线的选择晶体管。 字线驱动器耦合到字线。 字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。 无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。 无源元件对于字线和触点连接之间的漏电流是透射的。

公开(公告)号：US07196572B2

公开(公告)日：2007-03-27

申请号：US11123226

申请日：2005-05-06

申请人： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Jörg Kliewer

发明人： Ralf Schneider ,  Stephan Schröder ,  Manfred Pröll ,  Jörg Kliewer

IPC分类号： G05F1/10

CPC分类号： G11C11/4074 ,  G11C5/145

摘要： An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

摘要翻译： 集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。 包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。 控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值 输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。 结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。

公开(公告)号：US07158426B2

公开(公告)日：2007-01-02

申请号：US11121175

申请日：2005-05-04

申请人： Koen van der Zanden ,  Manfred Pröll ,  Jörg Kliewer ,  Björn Wirker

发明人： Koen van der Zanden ,  Manfred Pröll ,  Jörg Kliewer ,  Björn Wirker

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/12015 ,  G11C29/50012 ,  G11C2029/1204 ,  G11C2029/2602

摘要： An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

摘要翻译： 集成半导体存储器可以在与控制时钟同步的正常操作状态下操作。 在测试操作状态下，集成半导体存储器与第一控制信号的控制时钟的时钟边沿同步地驱动，并独立于控制时钟启动测试运行。 利用第一控制信号驱动，可以由存储体地址选择的存储体中的选择晶体管截止。 之后，所选择的存储体中的位线被互连并以预定的预充电势驱动。 在预充电时间过去之后，通过应用的字线地址选择一个字线，并且连接到所选字线的所选存储体中的选择晶体管导通。 独立于控制时钟的时钟周期设置和测试预充电时间。

公开(公告)号：US07428673B2

公开(公告)日：2008-09-23

申请号：US11214482

申请日：2005-08-29

申请人： Jörg Kliewer ,  Martin Versen

发明人： Jörg Kliewer ,  Martin Versen

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025

摘要： The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

摘要翻译： 本发明涉及一种用于确定具有布置在其上的至少一个部件的电路载体的导线配置的测试方法，其中部件中的内部线以规定的顺序连接到部件连接，并且其中部件连接被连接到 电路载体。 根据该方法，使用集成在该部件中的可控测试信号发生器将各个规定的测试信号施加到部件的每条内部线路。 施加到电路载体的连接的输出信号被分接。 此后，使用用于确定部件连接和电路载体连接之间的导线配置的外部测试装置，利用施加到部件的内部线路的相应测试信号来识别各个输出信号。

公开(公告)号：US07206980B2

公开(公告)日：2007-04-17

申请号：US11123221

申请日：2005-05-06

申请人： Jürgen Auge ,  Manfred Pröll ,  Jörg Kliewer ,  Frank Schroeppel

发明人： Jürgen Auge ,  Manfred Pröll ,  Jörg Kliewer ,  Frank Schroeppel

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/48

摘要： An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

摘要翻译： 集成半导体存储器包括具有存储有数据值的至少一个存储单元的存储单元阵列和具有计数器的评估电路。 在集成半导体存储器的测试期间，如果存储在存储单元中的数据值偏离期望值，则计数器的计数器读数被改变。 阈值由控制电路预先定义。 编程电路将输入侧的阈值与计数器的瞬时计数器读数进行比较。 如果计数器的计数器读数超过阈值，则编程元件从第一编程状态变为第二编程状态。 在测试结束之后，通过输出端读出编程元件的状态。 该方案可以推断集成半导体存储器的可能的故障原因。

公开(公告)号：US07068216B2

公开(公告)日：2006-06-27

申请号：US10816662

申请日：2004-04-02

申请人： Jörg Kliewer ,  Georg Weiss

发明人： Jörg Kliewer ,  Georg Weiss

IPC分类号： G01S7/40

CPC分类号： G01S13/343 ,  G01S7/352 ,  G01S7/4021 ,  G01S2007/356

摘要： A method for the linearization of frequency modulated continuous wave (FMCW) radar devices having non-linear, ramp-shaped, modulated transmitter frequency progression x(t). With this invention, a correction phase term for compensation of the phase error in the reception signal q(t) is calculated on the receiver side in this device.

摘要翻译： 一种用于线性化具有非线性，斜坡形调制发射机频率进展x（t）的调频连续波（FMCW）雷达装置的方法。 利用本发明，在该装置中的接收机侧计算用于补偿接收信号q（t）中的相位误差的校正相位项。

公开(公告)号：US20050281118A1

公开(公告)日：2005-12-22

申请号：US11140554

申请日：2005-05-27

申请人： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

发明人： Jörg Kliewer ,  Herbert Benzinger ,  Manfred Pröll ,  Stephan Schröder

IPC分类号： G11C8/00 ,  G11C8/08 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C11/4085 ,  G11C29/02 ,  G11C29/025 ,  G11C29/83 ,  G11C29/832 ,  G11C2029/1202 ,  H01L27/10891 ,  H01L27/10897

摘要： An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

摘要翻译： 集成半导体存储器包括至少一个字线和多个存储器单元。 每个存储单元具有耦合到字线的选择晶体管。 字线驱动器耦合到字线。 字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。 无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。 无源元件对于字线和触点连接之间的漏电流是透射的。

公开(公告)号：US06940775B2

公开(公告)日：2005-09-06

申请号：US10823608

申请日：2004-04-14

申请人： Ralf Schneider ,  Manfred Pröll ,  Georg Erhard Eggers ,  Jörg Kliewer

发明人： Ralf Schneider ,  Manfred Pröll ,  Georg Erhard Eggers ,  Jörg Kliewer

IPC分类号： G11C8/02 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C2211/4061

摘要： An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

摘要翻译： 集成动态存储器包括被组合以形成单独的可独立寻址单元的存储单元，以及用于控制存储器单元的刷新模式的控制电路。 存储单元可以刷新其存储单元格内容。 控制电路被设计成使得一个或多个单元的存储单元可以在更新周期中并行进行刷新模式。 控制电路基于温度参考值设置要在刷新周期中并行刷新的多个存储单元单元。 可以增加存储器芯片的最大可能工作温度，而不需要对存储器访问的额外限制。

公开(公告)号：US06840778B2

公开(公告)日：2005-01-11

申请号：US10340464

申请日：2003-01-10

申请人： Claus Engelhardt ,  Jörg Kliewer ,  Rupert Lukas ,  Jan Spitz

发明人： Claus Engelhardt ,  Jörg Kliewer ,  Rupert Lukas ,  Jan Spitz

IPC分类号： G01R1/04 ,  H01R12/70 ,  H05K7/10 ,  H01R12/00

CPC分类号： G01R1/0466 ,  H01R12/7076 ,  H01R2201/20 ,  H05K7/1023

摘要： A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic conditions in a real application environment. In practice, such components are normally firmly soldered in on a module carrier. Owing to the thermal load during soldering, this solution cannot always be used and, furthermore, the contacts that are made should be detachable. Commercially available contact bases with detachable contacts cannot be used, however, since their dimensions are too large and they do not fit in the available surface area on the module carrier. The novel contact base is sufficiently small that a plurality of contact bases can be arranged closely one next to the other in a row in a very small space on a module carrier. The module carrier has plug contacts to be plugged into a commercial socket in order to make contact.

摘要翻译： 特别是关于存储器组件分析的频繁问题是存储器组件必须在实际应用环境中的现实条件下进行测试。 实际上，这些组件通常牢固地焊接在模块载体上。 由于焊接时的热负荷，该溶液不能总是被使用，此外，制成的触点应该是可拆卸的。 不可以使用具有可拆卸接触件的市售接触基座，但是由于它们的尺寸太大并且它们不适合于模块载体上的可用表面积。 新颖的接触基底足够小，使得多个接触基底可以在模块载体上的非常小的空间中彼此紧邻地布置成一排。 模块托架具有插头接头以插入商业插座以便接触。