公开(公告)号：US07979642B2

公开(公告)日：2011-07-12

申请号：US12232188

申请日：2008-09-11

申请人： David Michael Bull ,  Emre Özer

发明人： David Michael Bull ,  Emre Özer

IPC分类号： G06F13/00

CPC分类号： G06F12/126 ,  G06F9/3806 ,  G06F9/3851

摘要： A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.

摘要翻译： 提供了一种数据处理装置，包括用于执行多个程序线程的处理电路。 至少一个存储单元在多个程序线程之间共享并且包括多个条目，每个条目用于存储与高优先级程序线程或较低优先级程序线程相关联的存储项目。 还提供了用于保存存储单元的多个块中的每一个的历史字段的历史存储器。 在检测到作为对较低优先级存储项目的该条目的分配的结果被从存储单元驱逐的高优先级存储项目时，包含该条目的块的历史字段填充有被驱逐的高优先级存储项目的指示 。 当稍后将高优先级存储项目分配给存储单元的所选条目时，执行所分配的高优先级存储项目与包含所选择的条目的块的历史字段中的指示之间的比较操作，并且在检测到 匹配条件与该条目相关联的锁定指示被设置为禁止进一步驱逐该高优先级存储项目。

公开(公告)号：US08037287B2

公开(公告)日：2011-10-11

申请号：US12076165

申请日：2008-03-14

申请人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F9/30

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。

公开(公告)号：US09519538B2

公开(公告)日：2016-12-13

申请号：US13067510

申请日：2011-06-06

申请人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/07 ,  G06F9/38

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.

摘要翻译： 具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 部分错误恢复可能是从指令流水线中刷新上游程序指令。 当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。 指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在 可用主存储元件来适当地捕获与以下程序指令对应的信号值。

公开(公告)号：US07895469B2

公开(公告)日：2011-02-22

申请号：US12285796

申请日：2008-10-14

申请人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

发明人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/00

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3869

摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

摘要翻译： 集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗） 基于错误。 流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。 该预测用于触发第二次错误恢复操作（部分流水线停止）。 该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

公开(公告)号：US08640008B2

公开(公告)日：2014-01-28

申请号：US13336428

申请日：2011-12-23

申请人： Guillaume Schon ,  Luca Scalabrino ,  Frederic Claude Marie Piry ,  David Michael Bull

发明人： Guillaume Schon ,  Luca Scalabrino ,  Frederic Claude Marie Piry ,  David Michael Bull

IPC分类号： H03M13/00

CPC分类号： G06F11/1407 ,  G06F11/1497

摘要： A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.

摘要翻译： 数据处理装置具有错误检测单元，每个错误检测单元被配置为如果与指令的执行相关联的信号的第一和第二采样不同，则生成错误信号。 错误值产生电路产生一个错误值，显示任何错误检测单元是否产生了错误信号。 误差值稳定电路执行稳定程序，包括重新采样误差值以消除亚稳态。 错误恢复电路如果错误值被确认则启动指令的重新执行。 计数电路与错误值相关联地保持计数器值，当误差值被产生并且每当在到达误差值稳定电路之前重新采样误差值时递减，计数器值被设置为预定值。 如果在错误值到达故障值稳定电路之前计数器值为零，则误差值会绕过稳定程序。

公开(公告)号：US08621272B2

公开(公告)日：2013-12-31

申请号：US12735339

申请日：2008-12-29

申请人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

发明人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

公开(公告)号：US20120131313A1

公开(公告)日：2012-05-24

申请号：US13067510

申请日：2011-06-06

申请人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。

公开(公告)号：US08185812B2

公开(公告)日：2012-05-22

申请号：US11636716

申请日：2006-12-11

申请人： Shidhartha Das ,  David Theodore Blaauw ,  David Michael Bull

发明人： Shidhartha Das ,  David Theodore Blaauw ,  David Michael Bull

IPC分类号： G06F11/00

CPC分类号： G06F11/1695 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.

摘要翻译： 集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。 可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

公开(公告)号：US20100064287A1

公开(公告)日：2010-03-11

申请号：US12458699

申请日：2009-07-21

申请人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

发明人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

IPC分类号： G06F9/30 ,  G06F11/07 ,  G06F9/46

CPC分类号： G06F9/3836 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/004 ,  G06F11/1405

摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.

摘要翻译： 处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。 执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。 调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

公开(公告)号：US20090282281A1

公开(公告)日：2009-11-12

申请号：US12285373

申请日：2008-10-02

申请人： David Michael Bull ,  Ganesh Suryanarayan Dasika

发明人： David Michael Bull ,  Ganesh Suryanarayan Dasika

IPC分类号： G06F11/07

CPC分类号： G06F11/004 ,  G06F9/3869 ,  G06F11/0793

摘要： To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one functional element. At least one functional element includes error detection/recovery circuitry. The flow of input values to the first evaluation stage in the compound functional unit is controlled so that the input values are changed at most every second clock cycle.

摘要翻译： 为了防止在具有错误检测和恢复机制的系统中发生短路径错误，将功能元件组合以形成包括至少两个评估阶段的复合功能单元，每个评估阶段包括至少一个功能元件。 至少一个功能元件包括错误检测/恢复电路。 对复合功能单元中的第一评估阶段的输入值的流程进行控制，使得输入值最多每隔一个时钟周期改变。