公开(公告)号：US09519538B2

公开(公告)日：2016-12-13

申请号：US13067510

申请日：2011-06-06

申请人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/07 ,  G06F9/38

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.

摘要翻译： 具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 部分错误恢复可能是从指令流水线中刷新上游程序指令。 当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。 指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在 可用主存储元件来适当地捕获与以下程序指令对应的信号值。

公开(公告)号：US07895469B2

公开(公告)日：2011-02-22

申请号：US12285796

申请日：2008-10-14

申请人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

发明人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/00

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3869

摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

摘要翻译： 集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗） 基于错误。 流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。 该预测用于触发第二次错误恢复操作（部分流水线停止）。 该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

公开(公告)号：US08037287B2

公开(公告)日：2011-10-11

申请号：US12076165

申请日：2008-03-14

申请人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F9/30

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。

公开(公告)号：US08639987B2

公开(公告)日：2014-01-28

申请号：US12929848

申请日：2011-02-18

申请人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das

发明人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/00

CPC分类号： G06F1/324 ,  G06F1/3296 ,  G06F11/076 ,  Y02D10/126 ,  Y02D10/172

摘要： A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry. An operating parameter controller is then arranged, in the continuous mode of operation, to control one or more performance controlling operating parameters of the data processing apparatus in dependence upon the control signal. This enables efficient and robust control of those operating parameters in response to changes in environmental conditions.

摘要翻译： 提供一种使用监视电路来控制数据处理装置的操作参数的数据处理装置和方法。 所述数据处理装置具有用于执行数据处理的功能电路，所述功能电路包括错误校正电路，其被配置为检测功能电路的操作中的错误并修复这些操作中的错误。 可调节监控电路监视指示功能电路内的信号传播延迟的变化的特性，并产生取决于被监测特性的控制信号。 在连续调谐模式操作中，可调谐监视电路根据由纠错电路检测到的错误的某些特性来修改监视特性和控制信号之间的相关性。 然后，在连续操作模式下，设置操作参数控制器，以根据控制信号控制数据处理装置的一个或多个性能控制操作参数。 这可以响应于环境条件的变化而对这些操作参数进行有效和鲁棒的控制。

公开(公告)号：US08639975B2

公开(公告)日：2014-01-28

申请号：US12926436

申请日：2010-11-17

申请人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das ,  Daniel Kershaw

发明人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das ,  Daniel Kershaw

IPC分类号： G06F11/00

CPC分类号： G06F11/0763 ,  H03M13/09

摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.

摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。

公开(公告)号：US20130002298A1

公开(公告)日：2013-01-03

申请号：US13067886

申请日：2011-07-01

申请人： David William Howard ,  David Michael Bull ,  Shidhartha Das

发明人： David William Howard ,  David Michael Bull ,  Shidhartha Das

IPC分类号： H03K19/00 ,  H03L7/00

CPC分类号： H03K3/0372 ,  H03K3/0375 ,  H03K5/1534

摘要： A D-type flip-flop 2 includes tristate inverter circuitry 4, 6 passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate 10 to slave storage circuitry 12. A transition detector 16 is coupled to the input node nm of the storage circuitry 8 and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.

摘要翻译： D型触发器2包括三态逆变器电路4,6将处理信号传递到存储电路8，处理信号从处理信号经由传输门10通过到从存储电路12.转换检测器16耦合到输入端 存储电路8的节点nm，并且用于在错误检测周期期间在该输入节点上检测到转换时产生误差信号。 该技术的其他形式可以提供时钟选通电路。

公开(公告)号：US08327118B2

公开(公告)日：2012-12-04

申请号：US12458699

申请日：2009-07-21

申请人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

发明人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/004 ,  G06F11/1405

摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.

摘要翻译： 处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。 执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。 调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

公开(公告)号：US20110302460A1

公开(公告)日：2011-12-08

申请号：US12801402

申请日：2010-06-07

申请人： Sachin Satish Idgunji ,  Shidhartha Das ,  David Michael Bull ,  Robert Campbell Aitken

发明人： Sachin Satish Idgunji ,  Shidhartha Das ,  David Michael Bull ,  Robert Campbell Aitken

IPC分类号： G06F11/07

CPC分类号： G01R31/3016

摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly.

摘要翻译： 提供了一种用于检测数据处理装置内接近的错误状况的装置和方法。 数据处理装置包括第二顺序存储结构，其被配置为根据第二时钟信号锁存由组合电路产生的输出信号。 第二顺序存储结构具有主存储元件，用于锁存输出信号的值以提供给后续组合电路;以及转换检测电路，用于检测由主存储元件在预定定时期间锁存的输出信号的值的变化 窗口，所述改变指示接近的错误状态，而存储在主存储元件中的值仍然是正确的。 第二顺序存储结构可以在第一操作模式或第二操作模式中操作。 在第一操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之前的定时窗口，从而使由于组合电路内的传播延迟引起的接近建立定时误差 被检测。 在第二操作模式中，预定定时窗口是在主存储元件锁存输出信号的值的时间之后的定时窗口，使得由于第一和第二时钟之间的偏斜增加而接近的保持定时误差 检测到信号。 这种技术提供了一种用于检测各种接近错误状况的简单有效的机制，同时第二序列存储结构继续正确地操作。

公开(公告)号：US07793082B2

公开(公告)日：2010-09-07

申请号：US11638703

申请日：2006-12-14

申请人： David Michael Bull ,  Shidhartha Das

发明人： David Michael Bull ,  Shidhartha Das

IPC分类号： G06F7/00

CPC分类号： G11C19/00

摘要： An integrated circuit includes processing pipeline stages formed of an input register, processing circuit and an output register. The output register employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry a transparent latch is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry. This transparent latch is non-transmissive during the speculation period of the output register so as to prevent any new signal propagating from the input register during the speculation period from reaching the output register.

摘要翻译： 集成电路包括处理由输入寄存器，处理电路和输出寄存器形成的流水线级。 输出寄存器采用推测采样，并使用随后的推测周期，在此期间检测其输入的任何变化并用于指示推测误差。 为了减少竞争条件的机会，由于通过处理电路的信号传播太快而引起误投影误差的错误正面检测，透明锁存器被设置在近似中点处，就传播延迟而言 处理电路。 该透明锁存器在输出寄存器的推测周期期间是不透明的，以便在推测期间防止任何新的信号从输入寄存器传播到达输出寄存器。

公开(公告)号：US08621272B2

公开(公告)日：2013-12-31

申请号：US12735339

申请日：2008-12-29

申请人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

发明人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.