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公开(公告)号：US07426629B2
公开(公告)日：2008-09-16
申请号：US10527960
申请日：2003-10-06
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.
摘要翻译： 数据处理系统具有这样的机制，即当数据值被存储在数据寄存器中时，另外的数据值存储在一个或多个另外的寄存器中，使得从高到低和从低到高的信号转换的总数量 不依赖于正在写入的数据值或先前的数据值而变化。
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公开(公告)号：US07313677B2
公开(公告)日：2007-12-25
申请号：US10527575
申请日：2003-10-06
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： Apparatus for processing data under control of data processing instructions specifying data processing operations, said apparatus comprising: a first execution mechanism operable to execute a first set of data processing instructions; a second execution mechanism operable to execute a second set of data processing instructions, said first set of data processing instructions overlapping with said second set of data processing instructions such that one or more data processing instructions are executable by either said first execution mechanism or said second execution mechanism; and an execution mechanism selector operable to pseudo randomly selected either said first execution mechanism or said second execution mechanism to execute one or more data processing instructions that are executable by either said first execution mechanism or said second execution mechanism.
摘要翻译： 用于在指定数据处理操作的数据处理指令的控制下处理数据的装置，所述装置包括：第一执行机构，可操作以执行第一组数据处理指令; 第二执行机构，其可操作以执行第二组数据处理指令，所述第一组数据处理指令与所述第二组数据处理指令重叠，使得一个或多个数据处理指令可由所述第一执行机构或所述第二执行机构执行 执行机制; 以及执行机构选择器，用于伪随机选择所述第一执行机构或所述第二执行机构，以执行可由所述第一执行机构或所述第二执行机构执行的一个或多个数据处理指令。
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3.发明授权Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution 有权遇到错误时，或通过在流水线等待队列中重新启动执行时刷新指令，可能会导致错误恢复公开(公告)号：US09075621B2
公开(公告)日：2015-07-07
申请号：US13336432
申请日：2011-12-23
申请人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
发明人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
CPC分类号： G06F9/3865 , G06F9/3855 , G06F9/3861 , G06F11/0736 , G06F11/0757 , G06F11/1405 , G06F11/1497
摘要： A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
摘要翻译： 数据处理装置以流水线执行阶段的顺序执行指令。 错误检测单元对与执行指令相关联的信号进行两次采样，并且如果样本不同则产生误差信号。 异常存储单元维护与发出到执行流水线的指令相对应的条目的年龄排序列表，并且可以标记条目以显示是否已经与该指令相关联地生成了错误信号。 定时器单元响应于产生误差信号以启动预定时间段的定时。 如果列表中的最旧的等待条目具有与其相关联地存储的所述错误标记，则错误恢复单元启动软管道冲洗过程，并且如果所述预定时间段过去则启动硬管道冲洗过程，所述硬冲洗程序包括将所述流水线重置为 预定状态。
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公开(公告)号：US20130151891A1
公开(公告)日：2013-06-13
申请号：US13313057
申请日：2011-12-07
IPC分类号： G06F11/07
CPC分类号： G06F11/0721 , G06F11/076 , G06F11/3024 , G06F11/3058
摘要： A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behaviour of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry.
摘要翻译： 一种数据处理装置，被配置为在电压和频率操作区域中操作，所述电压和频率操作区域位于不存在错误的安全区域之外，但是在操作区域限制内，使得错误是罕见的。 数据处理装置包括：错误检测电路和错误恢复电路; 所述错误检测电路被配置为确定在所述处理装置中采样的信号是否在所述信号被采样之后并且在与所述采样相同的时钟周期期间发生的时间窗内改变，并且如果所述信号确实改变则发送信号。 数据处理装置还包括性能控制电路，其被配置为确定数据处理装置何时操作接近错误率提高的操作区域限制，并且响应于确定接近操作区域限制的操作来修改数据的行为 处理装置中的至少一个：限制推测处理，以及选择不敏感时序的处理路径和电路。
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5.发明授权Handling of write access requests to shared memory in a data processing apparatus 有权在数据处理设备中处理对共享存储器的写访问请求公开(公告)号：US08271730B2
公开(公告)日：2012-09-18
申请号：US11907265
申请日：2007-10-10
申请人： Frederic Claude Marie Piry , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugéne Lataille , Stuart David Biles , Richard Roy Grisenthwaite
发明人： Frederic Claude Marie Piry , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugéne Lataille , Stuart David Biles , Richard Roy Grisenthwaite
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.
摘要翻译： 用于执行数据处理操作的多个处理单元需要访问共享存储器中的数据。 每个具有存储用于该处理单元访问的数据的子集的相关联的高速缓存。 缓存一致性协议确保每个单元访问的数据是最新的。 当输出用于存储在共享存储器中的数据值时，每个单元发出写访问请求。 当写访问请求需要更新相关联的高速缓存和共享存储器时，在高速缓存一致性逻辑内启动一致性操作。 对于包括与发出写访问请求的处理单元相关联的缓存的所有缓存执行一致性操作，以便确保这些高速缓存中的数据保持一致。
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6.发明授权Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation 有权高速缓存电路，数据处理装置和方法，用于通过选择第一预取行填充操作和第二预取行填充操作之一来预取数据公开(公告)号：US07917701B2
公开(公告)日：2011-03-29
申请号：US11716675
申请日：2007-03-12
申请人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
发明人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862
摘要： Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request.
摘要翻译： 提供预取电路，其响应于由当前访问请求指定的数据值的存储器地址与预测的存储器地址相同的确定，以执行第一预取行填充操作或第二预取行填充操作以从 记录至少一个另外的数据值，预期该数据值是后续访问请求的主题。 根据当前访问请求的属性执行第一预取行填充操作或第二预取行填充操作的选择。
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7.发明授权Executing variable length instructions stored within a plurality of discrete memory address regions 有权执行存储在多个离散存储器地址区域内的可变长度指令公开(公告)号：US07676652B2
公开(公告)日：2010-03-09
申请号：US10648293
申请日：2003-08-27
CPC分类号： G06F9/3816 , G06F9/30149 , G06F12/04
摘要： Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered. This execution is constrained by the setting of a single step flag which causes the hardware to only execute the single instruction which span the gap before returning control to a single step exception handler which can then restore program flow to the point in the following memory region after the variable length instruction which spanned the gap.
摘要翻译： 在支持执行可变长度指令的系统中，程序被存储在跨越两个这样的离散存储器区域之间的间隙的可变长度指令的离散存储器区域内。 当尝试跨越间隙的这种可变长度指令执行时，启动中止处理程序，其用于将其中一个存储器区域的端部与另一存储器区域的起始部分一起复制到单独的修正存储器区域 其中这些可以被级联，使得整个可变长度指令将出现在一个地方。 然后可以触发从固定存储区域中执行该可变长度指令。 该执行受到单步标志的设置的限制，这使得硬件仅在将控制返回到单步异常处理程序之前执行跨越间隙的单个指令，然后可以将程序流恢复到以下存储区域中的点 跨越差距的可变长度指令。
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公开(公告)号：US20080229070A1
公开(公告)日：2008-09-18
申请号：US11716675
申请日：2007-03-12
申请人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
发明人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862
摘要： Cache circuitry, a data processing apparatus including such cache circuitry, and a method for prefetching data into such cache circuitry, are provided. The cache circuitry has a cache storage comprising a plurality of cache lines for storing data values, and control circuitry which is responsive to an access racquet issued by a device of the data processing apparatus identifying a memory address of a data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. If not, a linefill operation is initiated to retrieve the data value from memory. Further, prefetch circuitry is provided which is responsive to a determination that the memory address specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request. The first prefetch linefill operation involves issuing a sequence of memory addresses to memory, and allocating into a corresponding sequence of cache lines the data values returned from the memory in response to that sequence of addresses. The second prefetch linefill operation comprises issuing a selected memory address to memory, and storing in a linefill buffer the at least one data value returned from the memory in response to that memory address, with that at least one data value only being allocated into the cache when a subsequent access request specifies the selected memory address. By such an approach, the operation of the prefetch circuitry can be altered to take into account the type of access request being issued.
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9.发明申请Reusing a buffer memory as a microcache for program instructions of a detected program loop 有权将缓冲存储器重新用作检测到的程序循环的程序指令的微存储器公开(公告)号：US20080172547A1
公开(公告)日：2008-07-17
申请号：US11652148
申请日：2007-01-11
申请人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Stephane Eric Sabastien Brochier , Gilles Eric Grandou
发明人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Stephane Eric Sabastien Brochier , Gilles Eric Grandou
IPC分类号： G06F9/32
CPC分类号： G06F9/381 , G06F9/3814
摘要： A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.
摘要翻译： 数据处理系统2包括具有相关联的缓冲存储器18,8的指令高速缓存6。 缓冲存储器18,8可以以缓冲模式或微存储模式工作。 在由环路检测器电路20执行的程序循环检测时，缓冲存储器切换到微型缓存模式。 当以微型缓存模式操作时，从缓冲存储器18,8读取指令数据，而不需要访问指令高速缓冲存储器6。
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公开(公告)号：US08738971B2
公开(公告)日：2014-05-27
申请号：US13313057
申请日：2011-12-07
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/076 , G06F11/3024 , G06F11/3058
摘要： A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behavior of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry.
摘要翻译： 一种数据处理装置，被配置为在电压和频率操作区域中操作，所述电压和频率操作区域位于不存在错误的安全区域之外，但是在操作区域限制内，使得错误是罕见的。 数据处理装置包括：错误检测电路和错误恢复电路; 所述错误检测电路被配置为确定在所述处理装置中采样的信号是否在所述信号被采样之后并且在与所述采样相同的时钟周期期间发生的时间窗内改变，并且如果所述信号确实改变则发送信号。 数据处理装置还包括性能控制电路，其被配置为确定数据处理装置何时操作接近错误率提高的操作区域限制，并且响应于确定接近操作区域限制的操作来修改数据的行为 处理装置中的至少一个：限制推测处理，以及选择不敏感时序的处理路径和电路。
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