公开(公告)号：US20120009759A1

公开(公告)日：2012-01-12

申请号：US13236751

申请日：2011-09-20

申请人： Dong-hoon JANG ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

发明人： Dong-hoon JANG ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519

摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。

公开(公告)号：US20100001366A1

公开(公告)日：2010-01-07

申请号：US12457813

申请日：2009-06-22

申请人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

发明人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

IPC分类号： H01L29/06

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519

摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。

公开(公告)号：US08486802B2

公开(公告)日：2013-07-16

申请号：US13236751

申请日：2011-09-20

申请人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

发明人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519

摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。

公开(公告)号：US08035152B2

公开(公告)日：2011-10-11

申请号：US12457813

申请日：2009-06-22

申请人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

发明人： Dong-hoon Jang ,  Young-bae Yoon ,  Hee-soo Kang ,  Young-seop Rah ,  Jeong-dong Choe

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519

摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。

公开(公告)号：US20090302472A1

公开(公告)日：2009-12-10

申请号：US12453961

申请日：2009-05-28

申请人： Young-bae Yoon ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

发明人： Young-bae Yoon ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L23/52

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11548

摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

摘要翻译： 提供了非易失性存储器件及其制造方法，包括改进的位线和接触形成，其可以降低电阻和寄生电容，从而降低制造成本并提高器件性能。 非易失性存储器件可以包括衬底; 形成在所述基板上的多个场区域，所述场区域中的每一个包括均匀的第一场和经由桥区域被划分为两个子区域的第二场; 形成在所述基板上的有源区，并且被定义为具有通过所述场区域的串结构，其中至少两个串可经由所述桥接区域之一连接; 并且可以在场区域上形成多个共享位线，并且经由位线触点连接到有源区，其中位线接触可以是直接接触。

公开(公告)号：US20120276729A1

公开(公告)日：2012-11-01

申请号：US13545711

申请日：2012-07-10

申请人： Young-bae YOON ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

发明人： Young-bae YOON ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L21/28

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11548

摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

摘要翻译： 提供了非易失性存储器件及其制造方法，包括改进的位线和接触形成，其可以降低电阻和寄生电容，从而降低制造成本并提高器件性能。 非易失性存储器件可以包括衬底; 形成在所述基板上的多个场区域，所述场区域中的每一个包括均匀的第一场和经由桥区域被划分为两个子区域的第二场; 形成在所述基板上的有源区，并且被定义为具有通过所述场区域的串结构，其中至少两个串可经由所述桥接区域之一连接; 并且可以在场区域上形成多个共享位线，并且经由位线触点连接到有源区，其中位线接触可以是直接接触。

公开(公告)号：US08426272B2

公开(公告)日：2013-04-23

申请号：US13545711

申请日：2012-07-10

申请人： Young-bae Yoon ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

发明人： Young-bae Yoon ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11548

摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

公开(公告)号：US08208301B2

公开(公告)日：2012-06-26

申请号：US12573239

申请日：2009-10-05

申请人： Hee-soo Kang ,  Choong-ho Lee ,  Yoon-moon Park ,  Dong-hoon Jang ,  Young-bae Yoon

发明人： Hee-soo Kang ,  Choong-ho Lee ,  Yoon-moon Park ,  Dong-hoon Jang ,  Young-bae Yoon

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings.

摘要翻译： 提供了具有公共位线结构的非易失性存储器件。 非易失性存储器件包括具有NAND单元阵列结构的多个单元元件，其布置在多个存储器串中的每一个中，并且每个都包括控制栅极和电荷存储层。 多个通用位线通常连接到存储器串中的一对存储器串的每一个的末端。 提供了具有与第一选择晶体管串联连接并且具有低于第一驱动电压的第二驱动电压的第一驱动电压和多个第二选择晶体管的第一选择晶体管。 第一选择晶体管和第二选择晶体管被布置在公共位线和存储器串的单位元件之间。

公开(公告)号：US20100085812A1

公开(公告)日：2010-04-08

申请号：US12573239

申请日：2009-10-05

申请人： Hee-soo Kang ,  Choong-ho Lee ,  Yoon-moon Park ,  Dong-hoon Jang ,  Young-bae Yoon

发明人： Hee-soo Kang ,  Choong-ho Lee ,  Yoon-moon Park ,  Dong-hoon Jang ,  Young-bae Yoon

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings. A first string selection line is connected to one of the first and second selection transistors of a first memory string of one pair of memory strings that are connected to one of the common bit lines. A second string selection line is connected to one of the first and second selection transistors of a second memory string of one pair of memory strings that are connected to one of the common bit lines. Multiple word lines are connected to control gates of the unit elements having the NAND cell array structure which are arranged in the same rows.

摘要翻译： 提供了具有公共位线结构的非易失性存储器件。 非易失性存储器件包括具有NAND单元阵列结构的多个单元元件，其布置在多个存储器串中的每一个中，并且每个都包括控制栅极和电荷存储层。 多个通用位线通常连接到存储器串中的一对存储器串的每一个的末端。 提供了具有与第一选择晶体管串联连接并且具有低于第一驱动电压的第二驱动电压的第一驱动电压和多个第二选择晶体管的第一选择晶体管。 第一选择晶体管和第二选择晶体管被布置在公共位线和存储器串的单位元件之间。 第一串选择线连接到连接到公共位线之一的一对存储器串的第一存储器串的第一和第二选择晶体管之一。 第二串选择线连接到连接到公共位线之一的一对存储器串的第二存储器串的第一和第二选择晶体管之一。 多个字线连接到具有排列在相同行中的具有NAND单元阵列结构的单元元件的控制栅极。

公开(公告)号：US20090309154A1

公开(公告)日：2009-12-17

申请号：US12486367

申请日：2009-06-17

申请人： Byung-kyu Cho ,  Hee-soo Kang ,  Dong-uk Choi ,  Choong-ho Lee

发明人： Byung-kyu Cho ,  Hee-soo Kang ,  Dong-uk Choi ,  Choong-ho Lee

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/11521

摘要： Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.

摘要翻译： 提供一种选择晶体管及其制造方法。 选择晶体管可以形成在半导体衬底中的有源区上，以包括栅极电极，该栅电极包括栅电极的侧壁的凹陷部分，该栅极电极的侧壁相对于栅电极的下部凹入，以限定T形截面 栅电极。 隧道绝缘层可以位于栅电极和有源区之间。