NON-VOLATILE MEMORY DEVICES INCLUDING SHARED BIT LINES AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    NON-VOLATILE MEMORY DEVICES INCLUDING SHARED BIT LINES AND METHODS OF FABRICATING THE SAME 有权
    包含共享位线的非易失性存储器件及其制造方法

    公开(公告)号:US20120276729A1

    公开(公告)日:2012-11-01

    申请号:US13545711

    申请日:2012-07-10

    IPC分类号: H01L21/28

    摘要: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

    摘要翻译: 提供了非易失性存储器件及其制造方法,包括改进的位线和接触形成,其可以降低电阻和寄生电容,从而降低制造成本并提高器件性能。 非易失性存储器件可以包括衬底; 形成在所述基板上的多个场区域,所述场区域中的每一个包括均匀的第一场和经由桥区域被划分为两个子区域的第二场; 形成在所述基板上的有源区,并且被定义为具有通过所述场区域的串结构,其中至少两个串可经由所述桥接区域之一连接; 并且可以在场区域上形成多个共享位线,并且经由位线触点连接到有源区,其中位线接触可以是直接接触。

    Non-volatile memory devices including shared bit lines and methods of fabricating the same
    3.
    发明申请
    Non-volatile memory devices including shared bit lines and methods of fabricating the same 审中-公开
    包括共享位线的非易失性存储器件及其制造方法

    公开(公告)号:US20090302472A1

    公开(公告)日:2009-12-10

    申请号:US12453961

    申请日:2009-05-28

    IPC分类号: H01L23/52

    摘要: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

    摘要翻译: 提供了非易失性存储器件及其制造方法,包括改进的位线和接触形成,其可以降低电阻和寄生电容,从而降低制造成本并提高器件性能。 非易失性存储器件可以包括衬底; 形成在所述基板上的多个场区域,所述场区域中的每一个包括均匀的第一场和经由桥区域被划分为两个子区域的第二场; 形成在所述基板上的有源区,并且被定义为具有通过所述场区域的串结构,其中至少两个串可经由所述桥接区域之一连接; 并且可以在场区域上形成多个共享位线,并且经由位线触点连接到有源区,其中位线接触可以是直接接触。

    Code generation and allocation apparatus
    6.
    发明授权
    Code generation and allocation apparatus 失效
    代码生成和分配设备

    公开(公告)号:US07616135B2

    公开(公告)日:2009-11-10

    申请号:US12027317

    申请日:2008-02-07

    IPC分类号: H03M7/00

    摘要: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

    摘要翻译: 一种产生和分配码字的方法包括:当前一个码字“a”和随后的码字“b”形成码流X时,将两个可选码字b1和b2之一分配为码字“b”,其中码字b1和b2具有 相反的INV值,其是指示码字中包含的“1”的数目是奇数还是偶数的参数。 当前一个码字“a”的码流和随后的码字b1为X1时,当前一个码字“a”和随后的码字b2的码流为X2时,分配码字,使得X1的INV值 并且当前面的码字“a”或者随后的码字b1(b2)(b1或b2)应该被替换为符合在码字之间给定的预定边界条件的另一码字时,X2被维持为相反。 分配码字使得能够维持码流的DC抑制能力。

    Soft demodulation method and apparatus
    7.
    发明授权
    Soft demodulation method and apparatus 失效
    软解调方法及装置

    公开(公告)号:US07369615B2

    公开(公告)日:2008-05-06

    申请号:US10763381

    申请日:2004-01-26

    IPC分类号: H04B14/06

    摘要: A soft demodulation method and apparatus including calculating partial sums for a unit of each predetermined number of bits of a codeword received from a channel; calculating a value of each entry of the decoding table by referring to the partial sums; and detecting a maximum among values of all entries of the decoding table and calculating a log-likelihood ratio (LLR) using the detected maximum. Accordingly, it is possible to reduce the amount of computation required to perform a soft demodulation process using run-length limited (RLL) codes and to simplify the soft demodulation process.

    摘要翻译: 一种软解调方法和装置,包括对从信道接收的码字的每个预定位数的单位计算部分和; 通过参考部分和来计算解码表的每个条目的值; 并且检测解码表的所有条目的值中的最大值,并使用检测到的最大值来计算对数似然比(LLR)。 因此,可以减少使用游程长度限制(RLL)码进行软解调处理所需的计算量并简化软解调处理。

    Method of converting parity check matrix for low density parity check coding
    8.
    发明授权
    Method of converting parity check matrix for low density parity check coding 失效
    用于低密度奇偶校验编码的奇偶校验矩阵的转换方法

    公开(公告)号:US07363570B2

    公开(公告)日:2008-04-22

    申请号:US11020017

    申请日:2004-12-23

    IPC分类号: H03M10/00

    CPC分类号: H03M13/1182

    摘要: A method of converting a parity check matrix for low density parity check coding comprising moving rows and columns of the parity check matrix such that the parity check matrix includes a lower triangular submatrix. A calculation load for creating parity information can be reduced by using the converted parity check matrix including the lower triangular submatrix.

    摘要翻译: 一种转换用于低密度奇偶校验编码的奇偶校验矩阵的方法,包括移动奇偶校验矩阵的行和列,使得奇偶校验矩阵包括下三角形子矩阵。 可以通过使用包括下三角子矩阵的转换奇偶校验矩阵来减少用于创建奇偶校验信息的计算负载。

    Stage apparatus
    9.
    发明授权
    Stage apparatus 有权
    舞台装置

    公开(公告)号:US07240434B2

    公开(公告)日:2007-07-10

    申请号:US11050761

    申请日:2005-02-07

    IPC分类号: G01B5/00

    CPC分类号: H02N2/0095 Y10S269/903

    摘要: A stage apparatus may include a first stage, a second stage movable with respect to the first stage, at least one flexure hinge to connect the first stage with the second stage, a plurality of actuators provided between the first stage and the second stage to push the first stage and the second stage and to be symmetric with respect to a center of the first stage and the second stage, and a controller to control the plurality of actuators to move one of the first stage and the second stage with respect to the other one of the first stage and the second stage. Thus, a position error of the stage can be reduced, which enables an ultra precision position control. Further, a piezoelectric driver using piezoelectric elements may be used as the actuator to decrease the position error more than a conventional driver such as a motor. The position error may be decreased to ±10 nm.

    摘要翻译: 平台装置可以包括第一阶段,相对于第一阶段可移动的第二阶段,至少一个挠曲铰链以将第一阶段与第二阶段连接;多个致动器,设置在第一阶段和第二阶段之间以推动 第一级和第二级,并且相对于第一级和第二级的中心对称,以及控制器,用于控制多个致动器相对于另一级移动第一级和第二级中的一者 第一阶段和第二阶段之一。 因此,能够减小平台的位置误差,能够进行超精密位置控制。 此外,使用压电元件的压电驱动器可以用作致动器,以比诸如电动机的常规驱动器更多地降低位置误差。 位置误差可能会降低到±10 nm。