-
1.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SHARED BIT LINE STRUCTURE 有权制造具有共享位线结构的半导体器件的方法公开(公告)号：US20120009759A1
公开(公告)日：2012-01-12
申请号：US13236751
申请日：2011-09-20
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519
摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.
摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。
-
2.发明申请Semiconductor device having shared bit line structure and method of manufacturing the same 有权具有共享位线结构的半导体器件及其制造方法公开(公告)号：US20100001366A1
公开(公告)日：2010-01-07
申请号：US12457813
申请日：2009-06-22
IPC分类号： H01L29/06
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519
摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.
摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。
-
3.发明授权Method of manufacturing semiconductor device having shared bit line structure 有权制造具有共享位线结构的半导体器件的方法公开(公告)号：US08486802B2
公开(公告)日：2013-07-16
申请号：US13236751
申请日：2011-09-20
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519
摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.
摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。
-
公开(公告)号：US08035152B2
公开(公告)日：2011-10-11
申请号：US12457813
申请日：2009-06-22
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519
摘要： A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.
摘要翻译： 一种半导体器件，包括具有第一和第二有源区的衬底，所述第一和第二有源区设置在隔离结构的相对侧上;以及位线，其电耦合到所述隔离结构上的所述第一有源区 区域和第二有源区域，并且电耦合到直接接触第一和第二有源区域中的至少一个的有源桥接图案，其中接触插塞电耦合到第一有源区域和第二有源区域，以及底表面 所述有源桥模式位于所述第一和第二有源区的顶表面之下。
-
5.发明申请SEMICONDUCTOR DEVICE AND METHOD OF FORMING PATTERNS FOR THE SEMICONDUCTOR DEVICE 有权半导体器件和形成半导体器件的图案的方法公开(公告)号：US20100155906A1
公开(公告)日：2010-06-24
申请号：US12573535
申请日：2009-10-05
申请人： Young-ho Lee , Jae-hwang Sim , Young-seop Rah
发明人： Young-ho Lee , Jae-hwang Sim , Young-seop Rah
IPC分类号： H01L29/06
CPC分类号： H01L27/105 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L21/76229 , H01L27/0207 , H01L27/11519 , H01L27/11526
摘要： Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.
摘要翻译： 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。
-
公开(公告)号：US08368182B2
公开(公告)日：2013-02-05
申请号：US12573535
申请日：2009-10-05
申请人： Young-ho Lee , Jae-hwang Sim , Young-seop Rah
发明人： Young-ho Lee , Jae-hwang Sim , Young-seop Rah
IPC分类号： H01L29/06
CPC分类号： H01L27/105 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L21/76229 , H01L27/0207 , H01L27/11519 , H01L27/11526
摘要： Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.
摘要翻译： 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.03 秒)
