公开(公告)号：US20140015702A1

公开(公告)日：2014-01-16

申请号：US13716063

申请日：2012-12-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jaewon NAM

IPC: H03M1/38

CPC classification number: H03M1/144 ,  H03M1/123 ,  H03M1/129 ,  H03M1/145 ,  H03M1/365 ,  H03M1/38 ,  H03M1/46

Abstract: An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

Abstract translation: 根据本发明构思的模拟 - 数字转换器可以包括输出第一和第二参考电压的参考电压产生电路; 解压缩部件，对模拟输入信号的振幅和第一和第二参考电压进行减压; 闪速ADC参照解压缩的第一和第二参考电压将解压缩的模拟输入信号转换成第一数字信号; 以及逐次逼近ADC，根据第一数字信号和第一和第二参考电压根据逐次逼近操作将模拟输入信号转换成第二数字信号。

公开(公告)号：US20140062554A1

公开(公告)日：2014-03-06

申请号：US13758991

申请日：2013-02-04

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jaewon NAM ,  Minki KIM

IPC: H03L7/07

CPC classification number: H03L7/07 ,  H03K2005/00065 ,  H03L7/0812

Abstract: A delay time control circuit is provided which includes a delay locked loop generating a second clock signal delayed by a predetermined time in response to a first clock signal; a plurality of delay circuits each receiving the first and second clock signals and outputting third and fourth clock signals in response to first and second digital clock signals; and a feedback control unit receiving the third and fourth clock signals to detect a delay time and generating the first and second digital control signals for compensating the detected delay time.

Abstract translation: 提供延迟时间控制电路，其包括响应于第一时钟信号产生延迟预定时间的第二时钟信号的延迟锁定环; 多个延迟电路，每个延迟电路接收第一和第二时钟信号，并响应于第一和第二数字时钟信号输出第三和第四时钟信号; 以及反馈控制单元，接收第三和第四时钟信号以检测延迟时间，并产生用于补偿检测到的延迟时间的第一和第二数字控制信号。