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    NEURON CIRCUIT WITH SYNAPTIC WEIGHT LEARNING
    1.
    发明公开
    NEURON CIRCUIT WITH SYNAPTIC WEIGHT LEARNING 审中-公开

    公开(公告)号：US20230289582A1

    公开(公告)日：2023-09-14

    申请号：US18084234

    申请日：2022-12-19

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Young Hwan BAE ,  Jae-Jin LEE ,  Tae Wook KANG ,  Sung Eun KIM ,  Kyung Jin BYUN ,  Kwang IL OH ,  In San JEON

    IPC: G06N3/063 ,  G06N3/049

    CPC classification number: G06N3/063 ,  G06N3/049

    Abstract: A neuron circuit including a first internal circuit that receives a plurality of spike input signals, generates a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and outputs a second sum value by adding a membrane potential value to the first sum value, a spike generating circuit that generates a spike output signal, a membrane potential generating circuit that generates the membrane potential value, a second internal circuit that counts a last spike time based on the spike output signal, and an online learning circuit that receives a last input time from the first internal circuit and performs LTP learning based on the last input time or receives the last spike time from the second internal circuit and performs LTD learning based on the last spike time.

    ENCODER AND OPERATION METHOD THEREOF
    8.
    发明申请
    ENCODER AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20230068675A1

    公开(公告)日：2023-03-02

    申请号：US17895532

    申请日：2022-08-25

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Eun KIM ,  Tae Wook KANG ,  Hyuk KIM ,  Young Hwan BAE ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE ,  In San JEON

    IPC: G06N3/063 ,  G06N3/04

    Abstract: Disclosed is an encoder including event layer outputs first and second event signals, weight layer applies first and second weights to the first and second event signals respectively, and provides the first event signal in which the first weight is applied and the second event signal in which the second weight is applied to first node, and first spike generation circuit generates first input spike signal of which firing period is changed based on voltage level of the first node. The voltage level of the first node is reduced continuously, increases for first voltage corresponding to the first weight in response to the first event signal activated, and increases for second voltage corresponding to the second weight in response to the second event signal activated.

    ELECTRONIC CIRCUIT FOR IMPLEMENTING GENERATIVE ADVERSARIAL NETWORK USING SPIKE NEURAL NETWORK
    9.
    发明申请
    ELECTRONIC CIRCUIT FOR IMPLEMENTING GENERATIVE ADVERSARIAL NETWORK USING SPIKE NEURAL NETWORK 审中-公开

    公开(公告)号：US20190392291A1

    公开(公告)日：2019-12-26

    申请号：US16445925

    申请日：2019-06-19

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Seong Mo PARK ,  Jae-Jin LEE ,  Sung Eun KIM ,  Kyung Hwan PARK ,  Mi Jeong PARK ,  Young Hwan BAE ,  Kwang IL OH ,  Byounggun CHOI

    IPC: G06N3/04

    Abstract: Provided is an electronic circuit for implementing a generative adversarial neural network. The electronic circuit includes a spike converter, a spike image generator, a spike image converter, and an image discriminator. The spike converter generates a first signal including spike signals. The number of the spike signals is determined based on first data associated with second data within a reference time interval. The spike image generator generates a second signal including spike signals being selected based on a weight among the spike signals of the first signal. The image converter converts the spike signals of the second signal to generate third data being represented in an analog domain. The image discriminator provides the spike image generator with result data being associated with a difference between a value of the third data and a value of the second data. The image generator determines the weight based on the result data.

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