公开(公告)号：US06958660B2

公开(公告)日：2005-10-25

申请号：US10754486

申请日：2004-01-09

Applicant: Francesco Adduci ,  Antonio Colaci

Inventor： Francesco Adduci ,  Antonio Colaci

IPC: H03B5/36 ,  H03C1/62

CPC classification number: H03B5/36

Abstract: A method for the determination of a bias current of a quartz oscillator that includes the phases of: defining a series of bias currents of prefixed values; supplying to said quartz oscillator a bias current value not yet used; verifying the presence of an oscillation signal at the output of said quartz oscillator; supplying in the negative case to said quartz oscillator a bias current value not yet used and repeating the preceding phase; verifying the presence of the correct oscillation frequency; supplying in the negative case a bias current not yet used to said quartz oscillator and repeating the phase of verifying the presence of an oscillation signal at the output of said quartz oscillator; storing, in the positive case, that the supplied current is valid; repeating the preceding phases up to the exhaustion of said series of values of bias currents; fixing as a bias current of said quartz oscillator the algebraic average of the currents regarded as valid.

Abstract translation: 一种用于确定石英振荡器的偏置电流的方法，其包括以下阶段：定义一系列预定值的偏置电流; 向所述石英振荡器供应尚未使用的偏置电流值; 验证在所述石英振荡器的输出处存在振荡信号; 在所述石英振荡器中向所述石英振荡器供给尚未使用的重复前一相的偏置电流值; 验证正确振荡频率的存在; 在负情况下提供尚未用于所述石英振荡器的偏置电流，并重复验证在所述石英振荡器的输出处存在振荡信号的相位; 在正面情况下存储所提供的电流是有效的; 重复前述相位直到所述一系列偏置电流值的耗尽; 固定为所述石英振荡器的偏置电流，所述电流的代数平均值被认为是有效的。

公开(公告)号：US5621361A

公开(公告)日：1997-04-15

申请号：US454922

申请日：1995-05-31

Applicant: Francesco Adduci

Inventor： Francesco Adduci

IPC: H03B5/36

CPC classification number: H03B5/364

Abstract: A one-pin integrated crystal oscillator in a Colpitts configuration employs a differential amplifier, provided with a feedback network, as an input gain stage. This achieves an enhanced stability and independence from temperature variation, a high Q figure, and a short start-up with a relatively small area of integration.

Abstract translation: Colpitts配置中的单针集成晶体振荡器采用带有反馈网络的差分放大器作为输入增益级。 这实现了增强的稳定性和独立于温度变化，高Q值以及具有相对小的积分面积的短启动。

公开(公告)号：US06522168B2

公开(公告)日：2003-02-18

申请号：US09943370

申请日：2001-08-29

Applicant: Francesco Adduci ,  Claudio Bona ,  Andrea Fassina

Inventor： Francesco Adduci ,  Claudio Bona ,  Andrea Fassina

IPC: H03K190175

CPC classification number: H03K3/356113 ,  H03K3/356165 ,  H03K17/102 ,  H03K19/003 ,  H03K19/007

Abstract: An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface a first circuit portion powered by a power supply having the first voltage level, a second circuit portion is powered by a power supply having a second voltage level, and a power supply detection circuit structured to accept a detection signal and to maintain a correct output at the output terminal even after the power supply having the first voltage level no longer supplies the first voltage level to the interface.

公开(公告)号：US08098720B2

公开(公告)日：2012-01-17

申请号：US11869661

申请日：2007-10-09

Applicant: Francesco Adduci

Inventor： Francesco Adduci

IPC: H04B3/46 ,  H04B15/00 ,  H04L25/03

CPC classification number: H04L25/0202

Abstract: A method detects multipath propagation in a modulated digital signal. The method provides a first value of channel frequency, representing the modulated digital signal free of multipath propagation, providing a second value of said channel frequency, representing the modulated digital signal with multipath propagation, and comparing the first and second values. A method detects adjacent channel interference in a modulated digital signal by comparing first and second values of a characteristic parameter of the digital signal, respectively representing the digital signal free of adjacent channel interference and the digital signal affected by adjacent channel interference. In particular, the method obtains a derivative signal, applies a non-linear Teager-Kaiser function to the digital signal and the derivative signal for generating first and second signals respectively representing energy content of the digital signal and energy content of the derivative signal, and processes the first and second signals for generating the second value.

Abstract translation: 一种方法检测调制数字信号中的多径传播。 该方法提供信道频率的第一值，表示没有多径传播的调制数字信号，提供所述信道频率的第二值，表示具有多径传播的调制数字信号，以及比较第一和第二值。 一种方法通过比较分别表示没有相邻信道干扰的数字信号和受相邻信道干扰影响的数字信号的数字信号的特征参数的第一和第二值来检测调制数字信号中的相邻信道干扰。 特别地，该方法获得导数信号，对数字信号和微分信号施加非线性Teager-Kaiser函数，以产生分别表示数字信号的能量含量和导数信号的能量含量的第一和第二信号，以及 处理用于产生第二值的第一和第二信号。

公开(公告)号：US06160416A

公开(公告)日：2000-12-12

申请号：US205037

申请日：1998-12-04

Applicant: Francesco Adduci ,  Fabrizio Stefani

Inventor： Francesco Adduci ,  Fabrizio Stefani

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K17/166 ,  H03K19/00361

Abstract: An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node. In one preferred method, the current is injected or taken by controlling a first driving circuit so as to inject a current into the output node or controlling a second driving circuit so as to take a current from the output node.

Abstract translation: 输出缓冲电路，包括输入节点，输出级，连接到输出级的输出节点，以及控制电路，其控制输出信号的上升沿和下降沿期间的电压变化。 控制电路比较输入信号和输出信号的电平并驱动输出级。 在优选实施例中，控制电路包括各自连接到输入和输出节点的第一和第二逻辑电路。 第一逻辑电路选择性地使第一驱动电路工作，第二逻辑电路有选择地使第二驱动电路工作。 另外，提供了一种在输出缓冲电路的输出信号的上升沿和下降沿期间进行压摆率控制的方法。 根据该方法，比较输出信号的电平和输入信号的电平。 如果输入和输出信号具有不同的电平，则将电流注入或从输出节点取出。 在一种优选的方法中，通过控制第一驱动电路来注入或取出电流，以将电流注入输出节点或控制第二驱动电路以便从输出节点获取电流。

公开(公告)号：US07463903B2

公开(公告)日：2008-12-09

申请号：US10653704

申请日：2003-09-02

Applicant: Gianluigi Boarin ,  Francesco Adduci ,  Mattia Oddicini ,  Salvatore Matteo Crudo

Inventor： Gianluigi Boarin ,  Francesco Adduci ,  Mattia Oddicini ,  Salvatore Matteo Crudo

IPC: H04M1/00

CPC classification number: H03K7/08 ,  H04B1/40 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/067

Abstract: The present invention relates to a high-speed interface for radio systems, in particular to a synchronous serial digital interface for a car radio. In an embodiment, the synchronous serial digital interface for at least dual radio receiver systems includes a master device and a slave device. The dual radio receiver system has an intermediate frequency. The master device and the slave device exchange data in a bi-directional manner on at least one communication channel; the master device and the slave device have a unique bit clock; the master device supplies a synchronization signal to the slave device. The synchronization signal has a frequency spectrum with an amplitude at the intermediate frequency lower than the amplitudes at the other frequencies of the synchronization signal.

Abstract translation: 本发明涉及用于无线电系统的高速接口，特别涉及用于汽车无线电的同步串行数字接口。 在一个实施例中，用于至少双无线电接收机系统的同步串行数字接口包括主设备和从设备。 双无线电接收机系统具有中频。 主设备和从设备在至少一个通信信道上以双向方式交换数据; 主设备和从设备具有唯一的位时钟; 主设备向从设备提供同步信号。 同步信号具有在中频的振幅低于同步信号的其他频率的振幅的频谱。

公开(公告)号：US20080084953A1

公开(公告)日：2008-04-10

申请号：US11869661

申请日：2007-10-09

Applicant: Francesco Adduci

Inventor： Francesco Adduci

IPC: H04B14/06

CPC classification number: H04L25/0202

Abstract: A method detects multipath propagation in a modulated digital signal. The method provides a first value of channel frequency, representing the modulated digital signal free of multipath propagation, providing a second value of said channel frequency, representing the modulated digital signal with multipath propagation, and comparing the first and second values. A method detects adjacent channel interference in a modulated digital signal by comparing first and second values of a characteristic parameter of the digital signal, respectively representing the digital signal free of adjacent channel interference and the digital signal affected by adjacent channel interference. In particular, the method obtains a derivative signal, applies a non-linear Teager-Kaiser function to the digital signal and the derivative signal for generating first and second signals respectively representing energy content of the digital signal and energy content of the derivative signal, and processes the first and second signals for generating the second value.

Abstract translation: 一种方法检测调制数字信号中的多径传播。 该方法提供信道频率的第一值，表示没有多径传播的调制数字信号，提供所述信道频率的第二值，表示具有多径传播的调制数字信号，以及比较第一和第二值。 一种方法通过比较分别表示没有相邻信道干扰的数字信号和受相邻信道干扰影响的数字信号的数字信号的特征参数的第一和第二值来检测调制数字信号中的相邻信道干扰。 特别地，该方法获得导数信号，对数字信号和微分信号施加非线性Teager-Kaiser函数，以产生分别表示数字信号的能量含量和导数信号的能量含量的第一和第二信号，以及 处理用于产生第二值的第一和第二信号。

公开(公告)号：US5821791A

公开(公告)日：1998-10-13

申请号：US730699

申请日：1996-10-11

Applicant: Maurizio Gaibotti ,  Francesco Adduci

Inventor： Maurizio Gaibotti ,  Francesco Adduci

IPC: H03K3/3562 ,  H03K3/289

CPC classification number: H03K3/35625

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths. Furthermore, a single clock signal is used to enable both master and slave sections. The ability to use a single clock signal without local regeneration coupled with minimizing the number of required components facilitates higher integrated circuit density and reduces power consumption.

Abstract translation: 公开并要求保护低功耗和高密度D触发器电路，特别是对于包括主器件部分和从器件部分的标准单元库。 主部分包括主锁存结构，将主锁存器结构连接到两个电源电压中的一个的主耦合电路，以及用于将数据应用于触发器的输入耦合电路。 从部分包括直接插入在两个电源电压之间的从锁存结构，以及将从锁存结构连接到主锁存结构的从耦合电路。 通过扩大输入耦合电路中的晶体管的源极面积，实现本发明的D触发器电路实现所需的晶体管的数量被最小化，这导致大的寄生电容并确保主锁存器的最佳操作。 此外，从锁存结构中的晶体管具有非最小栅极长度。 此外，单个时钟信号用于启用主和从部分。 使用无需本地再生的单个时钟信号与最小化所需组件数量的能力有助于实现更高的集成电路密度并降低功耗。