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11 条记录 (耗时 0.017 秒)

    Scannable fuse latches
    3.
    发明授权
    Scannable fuse latches 失效
    可擦除保险丝锁存器

    公开(公告)号：US06201750B1

    公开(公告)日：2001-03-13

    申请号：US09598427

    申请日：2000-06-21

    申请人： Robert E. Busch ,  Fred J. Towler ,  Reid A. Wistort

    发明人： Robert E. Busch ,  Fred J. Towler ,  Reid A. Wistort

    IPC分类号： G11C700

    CPC分类号： G01R31/318541 ,  G11C17/16 ,  G11C17/18

    摘要： Scannable fuse latches are provided that can override current fuse values, read current fuse values, and latch current fuse values. Using the scannable fuse latches of the current invention allows current fuse values to be overridden, which can be important in testing and failure analysis to place the integrated circuit in a known state. The scannable fuse latches of the current invention also allow current fuse values to be read. This aids failure analysis because the current state of the failed integrated circuit can be determined. Finally, the scannable fuse latches of the present invention allow the current state of fuses to be latched and provided to a core of an integrated circuit.

    摘要翻译： 提供了可以提供可以覆盖当前熔丝值，读取当前熔丝值和锁存当前熔丝值的可擦除保险丝锁存器。 使用本发明的可扫描的熔丝锁存器允许覆盖当前熔丝值，这对于将集成电路置于已知状态的测试和故障分析中可能是重要的。 本发明的可扫描的熔丝锁存器还允许读取当前熔丝值。 这有助于故障分析，因为可以确定故障集成电路的当前状态。 最后，本发明的可扫描熔丝锁存器允许保险丝的当前状态被锁存并提供给集成电路的核心。

    Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances
    4.
    发明授权
    Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances 有权
    内容可寻址存储器（CAM）具有具有选择性可调的上拉阻抗的匹配线路电路

    公开(公告)号：US06697277B2

    公开(公告)日：2004-02-24

    申请号：US10421963

    申请日：2003-04-23

    申请人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

    发明人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

    IPC分类号： G11C1500

    CPC分类号： G11C29/50008 ,  G11C15/00 ,  G11C15/04 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002

    摘要： A match line circuit in a content addressable memory (CAM) has a match line coupled to a first pull-up device and a first pull-down device at a match node. The first pull-up device has selectively adjustable pull-up impedances associated with it. The match line circuit also includes a second pull-up device coupled to a second pull-down device at a float node, and an enabling signal for activating the match line circuit during a memory comparison operation. The enabling signal precharges the match node to a logic low level and the float node to a logic high level in between memory comparison operations.

    摘要翻译： 内容可寻址存储器（CAM）中的匹配线路电路具有耦合到匹配节点处的第一上拉设备和第一下拉设备的匹配线。 第一上拉装置具有与其相关联的选择性可调的上拉阻抗。 匹配线电路还包括耦合到浮动节点处的第二下拉装置的第二上拉装置，以及用于在存储器比较操作期间激活匹配线电路的使能信号。 启用信号将匹配节点预充电到逻辑低电平，并将浮点节点在存储器比较操作之间进行逻辑高电平。

    Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)
    5.
    发明授权
    Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM) 失效
    用于调整内容可寻址存储器（CAM）的控制电路上拉余量的方法和装置

    公开(公告)号：US06618279B2

    公开(公告)日：2003-09-09

    申请号：US09922893

    申请日：2001-08-06

    申请人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

    发明人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

    IPC分类号： G11C1500

    CPC分类号： G11C29/50008 ,  G11C15/00 ,  G11C15/04 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002

    摘要： A method for determining a desired operating impedance for a computer memory circuit includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.

    摘要翻译： 一种用于确定计算机存储器电路的期望工作阻抗的方法包括将参考电路的测试阻抗值应用于参考电路。 测试阻抗值由二进制计数控制。 基于所应用的测试阻抗值，确定参考电路是处于第一状态还是第二状态。 如果参考电路处于第一状态，则二进制计数递增，如果参考电路处于第二状态则递减。 确定参考电路在第一状态和所述第二状态之间振荡的条件，并存储一对二进制计数值。 计算机存储器电路的期望工作阻抗对应于存储的一对二进制计数值中的较低者。

    Low power CAM match line circuit
    7.
    发明授权
    Low power CAM match line circuit 失效
    低功率CAM匹配线路电路

    公开(公告)号：US06373738B1

    公开(公告)日：2002-04-16

    申请号：US09716511

    申请日：2000-11-20

    申请人： Fred J. Towler ,  Reid A. Wistort

    发明人： Fred J. Towler ,  Reid A. Wistort

    IPC分类号： G11C1500

    CPC分类号： G11C15/04

    摘要： A Match-Detection Circuit and Match-Detection method, for low-power-consuming searches in a Content Addressable Memory. A HIT is output when the Match Line rises from a Low voltage level to a higher Match Detection Voltage. The Match Detection Voltage is approximately the conducting threshold voltage of an N-channel Field Effect Transistor (FET), and is normally less than One Half of the Power Supply Voltage. Circuits and methods to turn of the through-current in each MISS-ing entry by a carefully timed control signal at the end of a brief Match Detection Period, are disclosed.

    摘要翻译： 匹配检测电路和匹配检测方法，用于内容寻址存储器中的低功耗搜索。 当匹配线从低电平电平上升到更高的匹配检测电压时，输出HIT。 匹配检测电压近似为N沟道场效应晶体管（FET）的导通阈值电压，通常小于电源电压的一半。 公开了在简短匹配检测周期结束时通过仔细定时的控制信号在每个MISS输入条目中转换通流的电路和方法。

    APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARRAYS
    8.
    发明申请
    APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARRAYS 有权
    用于静态随机访问存储器阵列的写入辅助装置和方法

    公开(公告)号：US20090235171A1

    公开(公告)日：2009-09-17

    申请号：US12048237

    申请日：2008-03-14

    申请人： Chad A. Adams ,  George M. Braceras ,  Harold Pilo ,  Fred J. Towler

    发明人： Chad A. Adams ,  George M. Braceras ,  Harold Pilo ,  Fred J. Towler

    IPC分类号： G06F3/00

    CPC分类号： G11C7/12 ,  G11C7/1096 ,  G11C11/419

    摘要： An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches.

    摘要翻译： 一种用于实现对存储器阵列的写入辅助的装置包括：公共放电节点，被配置为提供用于在存储器阵列的写入操作期间选择的预充电写入数据线和位线的放电路径; 负升压电路，被配置为在公共放电节点放电之后，在公共放电节点上引入低于标称逻辑低电源电压的电压，写入数据线和位线; 以及耦合到公共放电节点的钳位装置，所述钳位装置被配置为通过所述负升压电路限制施加到公共放电节点的负电压的幅值，以防止未选择的位开关的激活。

    Apparatus and method for implementing write assist for static random access memory arrays
    9.
    发明授权
    Apparatus and method for implementing write assist for static random access memory arrays 有权
    用于实现静态随机存取存储器阵列的写入辅助的装置和方法

    公开(公告)号：US08233342B2

    公开(公告)日：2012-07-31

    申请号：US12048237

    申请日：2008-03-14

    申请人： Chad A. Adams ,  George M. Braceras ,  Harold Pilo ,  Fred J. Towler

    发明人： Chad A. Adams ,  George M. Braceras ,  Harold Pilo ,  Fred J. Towler

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/1096 ,  G11C11/419

    摘要： An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches.

    摘要翻译： 一种用于实现对存储器阵列的写入辅助的装置包括：公共放电节点，被配置为提供用于在存储器阵列的写入操作期间选择的预充电写入数据线和位线的放电路径; 负升压电路，被配置为在公共放电节点放电之后，在公共放电节点上引入低于标称逻辑低电源电压的电压，写入数据线和位线; 以及耦合到公共放电节点的钳位装置，所述钳位装置被配置为通过所述负升压电路限制施加到公共放电节点的负电压的幅值，以防止未选择的位开关的激活。

    Method and apparatus for identifying SRAM cells having weak pull-up PFETs
    10.
    发明授权
    Method and apparatus for identifying SRAM cells having weak pull-up PFETs 失效

    公开(公告)号：US06552941B2

    公开(公告)日：2003-04-22

    申请号：US09902813

    申请日：2001-07-11

    申请人： Robert C. Wong ,  Fred J. Towler

    发明人： Robert C. Wong ,  Fred J. Towler

    IPC分类号： G11C700

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/5004

    摘要： A method for determining the memory cell stability of individual memory cells included within a memory array is disclosed. In an exemplary embodiment, the method includes presetting each memory cell to a first logic state and then applying a gradually increasing, controlled leakage current to a node within each memory cell. The voltage of each of the nodes within each corresponding memory cell is then monitored. Then, for each memory cell within the memory array, the level of leakage current which causes the memory cell to be changed from the first logic state to a second logic state is determined. The level of leakage current which causes the memory cell to be changed from the first logic state to the second logic state corresponds to the threshold voltage of a pull-up PFET within the memory cell.